Samsung S5PC110 Manual page 1050

S5PC110_UM
7.10.13 NORMAL INTERRUPT STATUS ENABLE REGISTER
7.10.13.1 Normal Interrupt Status Enable Register
•
NORINTSTSEN0, R/W, Address = 0xEB00_0034
•
NORINTSTSEN1, R/W, Address = 0xEB10_0034
•
NORINTSTSEN2, R/W, Address = 0xEB20_0034
•
NORINTSTSEN3, R/W, Address = 0xEB30_0034
Setting to 1 enables Interrupt Status.
NORINTSTSEN
-
ENSTAFIA3
ENSTAFIA2
ENSTAFIA1
ENSTAFIA0
ENSTARWAIT
ENSTACCS
ENSTACARDINT
ENSTACARDREM
Bit
[15] Fixed to 0
The Host Driver controls error interrupts using the Error
Interrupt Status Enable register. (R)
[14] FIFO SD Address Pointer Interrupt 3 Status Enable
1 = Enabled
0 = Masked
[13] FIFO SD Address Pointer Interrupt 2 Status Enable
1 = Enabled
0 = Masked
[12] FIFO SD Address Pointer Interrupt 1 Status Enable
1 = Enabled
0 = Masked
[11] FIFO SD Address Pointer Interrupt 0 Status Enable
1 = Enabled
0 = Masked
[10] Read Wait interrupt status enable
1 = Enabled
0 = Masked
[9] CCS Interrupt Status Enable
1 = Enabled
0 = Masked
[8] Card Interrupt Status Enable
If this bit is set to 0, the Host Controller clears interrupt
request to the System. The Card Interrupt detection is
stopped if this bit is cleared and restarted if this bit is set to
1. The Host Driver must clear the Card Interrupt Status
Enable before servicing the Card Interrupt and must set
this bit again after all interrupt requests from the card are
cleared to prevent inadvertent interrupts.
1 = Enabled
0 = Masked
[7] Card Removal Status Enable
1 = Enabled
0 = Masked
Description
7 SD/MMC CONTROLLER
Initial State
0
0
0
0
0
0
0
0
0
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