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TMS320C6670
Texas Instruments TMS320C6670 Manuals
Manuals and User Guides for Texas Instruments TMS320C6670. We have
3
Texas Instruments TMS320C6670 manuals available for free PDF download: Data Manual, Quick Start Manual
Texas Instruments TMS320C6670 Data Manual (226 pages)
Multicore Fixed and Floating-Point System-on-Chip
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 2.47 MB
Table of Contents
Table of Contents
3
1 TMS320C6670 Features
13
Keystone Architecture
14
Device Description
14
Functional Block Diagram
16
2 Device Overview
17
Device Characteristics
17
Characteristics of the C6670 Soc
17
Figure 2-1 CPU (DSP Core) Data Paths
20
Memory Map Summary
21
Table 2-1 Table
21
Table 2-6 Table
22
Table
23
Boot Sequence
29
Boot Modes Supported and PLL Settings
30
Boot Device Field
30
Device Configuration Field
31
Table 2-4 no Boot Configuration Field Descriptions
31
Table 2-5 Serial Rapid I/O Configuration Field Descriptions
31
Figure 2-5 Ethernet (SGMII) Device Configuration Fields
32
Table 2-9 I 2 C Master Mode Device Configuration Field Descriptions
33
Table 2-10 I 2 C Passive Mode Device Configuration Field Descriptions
34
Table 2-11 SPI Device Configuration Field Descriptions
34
Figure 2-9 SPI Device Configuration Fields
34
PLL Settings
35
Table 2-12 Hyperlink Boot Device Configuration Field Descriptions
35
Second-Level Bootloaders
36
Terminals
36
Package Terminals
36
Pin Map
36
Figure 2-13 Upper Left Quadrant—A (Bottom View)
37
Figure 2-14 Upper Right Quadrant—B (Bottom View)
38
Figure 2-15 Lower Right Quadrant—C (Bottom View)
39
Figure 2-16 Lower Left Quadrant—D (Bottom View)
40
Terminal Functions
41
Table 22-1415 Terminal Functions 2-14 Signals and Control by Function
41
Table 2-16 Terminal Functions - Power and Ground
52
Table 2-18 Terminal Functions - by Ball Number
57
Development
64
Development Support
64
Device Support
64
Figure 2-17 C66X™ DSP Device Nomenclature (Including the TMS320C6670 DSP)
65
Related Documentation from Texas Instruments
66
3 Device Configuration
67
Device Configuration at Device Reset
67
Peripheral Selection after Device Reset
68
Device State Control Registers
68
Device Status (DEVSTAT) Register
71
Device Configuration Register
72
Table 3-3 Device Status Register Field Descriptions
72
Table 3-4 Device Configuration Register Field Descriptions
72
JTAG ID (JTAGID) Register Description
73
Kicker Mechanism (KICK0 and KICK1) Register
73
LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
73
LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
74
Table 3-6 LRESETNMI PIN Status Register Field Descriptions
74
Table 3-7 LRESETNMI PIN Status Clear Register Field Descriptions
74
Reset Status (RESET_STAT) Register
75
Reset Status Clear (RESET_STAT_CLR) Register
75
Boot Complete (BOOTCOMPLETE) Register
76
Table 3-9 Reset Status Clear Register Field Descriptions
76
Table 3-10 Boot Complete Register Field Descriptions
76
Power State Control (PWRSTATECTL) Register
77
NMI Event Generation to Corepac (Nmigrx) Register
77
Table 3-11 Power State Control Register Field Descriptions
77
IPC Generation (Ipcgrx) Registers
78
Table 3-12 NMI Generation Register Field Descriptions
78
Table 3-13 IPC Generation Registers Field Descriptions
78
IPC Acknowledgement (Ipcarx) Registers
79
IPC Generation Host (IPCGRH) Register
79
Table 3-14 IPC Acknowledgement Registers Field Descriptions
79
IPC Acknowledgement Host (IPCARH) Register
80
Timer Input Selection Register (TINPSEL)
80
Table 3-15 IPC Generation Registers Field Descriptions
80
Table 3-16 IPC Acknowledgement Register Field Descriptions
80
Timer Output Selection Register (TOUTPSEL)
82
Table 3-18 Timer Output Selection Field Description
82
Reset Mux (Rstmuxx) Register
83
Device Speed (DEVSPEED) Register
84
Table 3-20 Device Speed Register Field Descriptions
84
Pullup/Pulldown Resistors
85
4 System Interconnect
86
Internal Buses and Switch Fabrics
86
Switch Fabric Connections Matrix
87
Table 4-1 Switch Fabric Connection Matrix Section 1
87
Table 4-2 Switch Fabric Connection Matrix Section 2
88
Table 4-3 Switch Fabric Connection Matrix Section 3
89
Teranet Switch Fabric Connections
91
Figure 4-2 Teranet 2A
92
Figure 4-3 Teranet 3P and 3M and 2M
93
Figure 4-4 Teranet 3P_A
94
Figure 4-5 Teranet 3P_B
95
Figure 4-6 Teranet 6P_B and 3P_Tracer
96
Bus Priorities
97
Table 4-4 Packed DMA Priority Allocation Register Field Descriptions
97
5 C66X Corepac
98
Memory Architecture
99
L1P Memory
99
L1D Memory
100
L2 Memory
101
Msm Sram
102
L3 Memory
102
Memory Protection
102
Bandwidth Management
103
Table 5-1 Available Memory Page Protection Schemes
103
Power-Down Control
104
Corepac Revision
104
C66X Corepac Register Descriptions
104
Table 5-2 Corepac Revision ID Register (MM_REVID) Field Descriptions
104
6 Device Operating Conditions
105
Absolute Maximum Ratings
105
Recommended Operating Conditions
106
Table 6-2 Recommended Operating Conditions
106
Electrical Characteristics
107
Power Supply to Peripheral I/O Mapping
108
Table 6-4 Power Supply to Peripheral I/O Mapping
108
7 TMS320C6670 Peripheral Information and Electrical Specifications
109
Recommended Clock and Control Signal Transition Behavior
109
Power Supplies
109
Power-Up Sequencing
110
Figure 7-1 Core before IO Power Sequencing
111
Figure 7-2 IO before Core Power Sequencing
113
Power-Down Sequence
115
Power Supply Decoupling and Bulk Capacitors
115
Table 7-2 Table
115
Smartreflex
116
Table 7-5 Smartreflex 4-Pin VID Interface Switching Characteristics
116
Power Sleep Controller (PSC)
117
Power Domains
117
Clock Domains
118
PSC Register Memory Map
119
Reset Controller
122
Power-On Reset
122
Hard Reset
123
Soft Reset
124
Local Reset
124
Reset Priority
125
Reset Controller Register
125
Reset Electrical Data/Timing
126
Table 7-12 Boot Configuration Timing Requirements
127
Main PLL and the PLL Controller
128
Main PLL Controller Device-Specific Information
129
Table 7-13 Main PLL Stabilization, Lock, and Reset Times
130
PLL Controller Memory Map
131
Table 7-14 PLL Controller Registers (Including Reset Controller)
131
Table 7-15 PLL Secondary Control Register Field Descriptions
132
Table 7-16 PLL Controller Divider Register Field Descriptions
133
Table 7-17 PLL Controller Clock Align Control Register Field Descriptions
133
Figure 7-9 PLL Controller Divider Register (Plldivn)
133
Table 7-18 PLLDIV Divider Ratio Change Status Register Field Descriptions
134
Table 7-20 Reset Type Status Register Field Descriptions
135
Figure 7-13 Reset Type Status Register (RSTYPE)
135
Table 7-21 Reset Control Register Field Descriptions
136
Table 7-22 Reset Configuration Register Field Descriptions
136
Figure 7-14 Reset Control Register (RSTCTRL)
136
Table 7-23 Reset Isolation Register Field Descriptions
137
Figure 7-16 Reset Isolation Register (RSISO)
137
Main PLL Control Registers
138
Table 7-24 Main PLL Control Register (MAINPLLCTL0) Field Descriptions
138
Table 7-25 Main PLL Control Register (MAINPLLCTL1) Field Descriptions
138
Main PLL and PLL Controller Initialization Sequence
139
Main PLL Controller/Srio/Hyperlink/Pcie Clock Input Electrical Data/Timing
139
Table 7-26 Main PLL Controller/Srio/Hyperlink/Pcie Clock Input Timing Requirements
139
Figure 7-19 Main PLL Controller/Srio/Hyperlink/Pcie Clock Input Timing
141
Ddr3 Pll
142
DDR3 PLL Control Registers
142
DDR3 PLL Device-Specific Information
143
DDR3 PLL Initialization Sequence
143
Table 7-27 DDR3 PLL Control Register 0 Field Descriptions
143
Table 7-28 DDR3 PLL Control Register 1 Field Descriptions (DDR3PLLCTL1)
143
DDR3 PLL Input Clock Electrical Data/Timing
144
Pass Pll
144
Table 7-29 DDR3 PLL DDRCLK(N|P) Timing Requirements
144
PASS PLL Control Registers
145
PASS PLL Device-Specific Information
146
PASS PLL Initialization Sequence
146
Table 7-30 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0)
146
Table 7-31 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1)
146
PASS PLL Input Clock Electrical Data/Timing
147
Enhanced Direct Memory Access (EDMA3) Controller
148
EDMA3 Device-Specific Information
149
EDMA3 Channel Controller Configuration
149
EDMA3 Transfer Controller Configuration
149
Table 7-33 EDMA3 Channel Controller Configuration
149
EDMA3 Channel Synchronization Events
150
Table 7-34 EDMA3 Transfer Controller Configuration
150
Interrupts
155
Interrupt Sources and Interrupt Controller
155
Table 7-38 System Event Mapping - C66X Corepac Primary Interrupts
156
Figure 7-29 Interrupt Topology
156
Table 7-39 CIC0 Event Inputs - C66X Corepac Secondary Interrupts
160
Table 7-40 CIC1 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2)
165
Table 7-41 CIC2 Event Inputs (Secondary Events for EDMA3CC0 and Hyperlink)
169
CIC Registers
170
Inter-Processor Register Map
176
NMI and LRESET
177
External Interrupts Electrical Data/Timing
178
Memory Protection Unit (MPU)
179
MPU Registers
182
Figure 7-31 Configuration Register (CONFIG)
187
MPU Programmable Range Registers
189
Table 7-59 Programmable Range N Start Address Register Field Descriptions
189
Table 7-60 Programmable Range N Start Address Register (Progn_Mpsar) Reset Values
189
Table 7-61 Programmable Range N End Address Register Field Descriptions
190
Table 7-62 Programmable Range N End Address Register (Progn_Mpear) Reset Values
190
Table 7-63 Programmable Range N Memory Protection Page Attribute Register Field Descriptions
191
Table 7-64 Programmable Range N Memory Protection Page Attribute Register (Progn_Mppa) Reset Values
193
DDR3 Memory Controller
194
DDR3 Memory Controller Device-Specific Information
194
DDR3 Memory Controller Electrical Data/Timing
195
I 2 C Peripheral
195
I 2 C Device-Specific Information
195
I 2 C Peripheral Register Description(S)
196
Table 7-65 I 2 C Registers
196
I 2 C Electrical Data/Timing
198
Table 7-66 I 2 C Timing Requirements
198
Table 7-67 I 2 C Switching Characteristics
199
SPI Peripheral
200
SPI Electrical Data/Timing
200
Figure 7-38 SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode
202
Hyperlink Peripheral
203
Table 7-70 Hyperlink Peripheral Timing Requirements
203
Table 7-71 Hyperlink Peripheral Switching Characteristics
203
Figure 7-40 Hyperlink Station Management Clock Timing
204
UART Peripheral
205
Pcie Peripheral
206
Packet Accelerator
206
Security Accelerator
207
Gigabit Ethernet (Gbe) Switch Subsystem
207
Figure 7-49 RFTCLK Select Register (CPTS_RFTCLK_SEL)
208
Management Data Input/Output (MDIO)
209
Timers
210
Timers Device-Specific Information
210
Timers Electrical Data/Timing
210
Table 7-80 Timer Output Switching Characteristics
210
Rake Search Accelerator (RSA)
211
Enhanced Viterbi-Decoder Coprocessor (VCP2)
211
Turbo Decoder Coprocessor (Tcp3D)
211
Turbo Encoder Coprocessor (Tcp3E)
211
Bit Rate Coprocessor (BCP)
212
Serial Rapidio (SRIO) Port
212
General-Purpose Input/Output (GPIO)
212
GPIO Device-Specific Information
212
GPIO Electrical Data/Timing
212
Table 7-82 GPIO Output Switching Characteristics
212
Semaphore2
213
Antenna Interface Subsystem 2 (AIF2)
213
Table 7-83 AIF2 Timer Module Timing Requirements
214
Figure 7-54 AIF2 RP1 Frame Synchronization Clock Timing
214
Receive Accelerator Coprocessor (RAC)
215
Table 7-84 AIF2 Timer Module Switching Characteristics
215
Transmit Accelerator Coprocessor (TAC)
216
Fast Fourier Transform Coprocessor (FFTC)
216
Emulation Features and Capability
216
Advanced Event Triggering (AET)
216
Trace
217
Ieee 1149.1 Jtag
217
A Revision History
219
B Mechanical Data
221
Thermal Data
221
Packaging Information
221
Table B-1 Thermal Resistance Characteristics (PBGA Package) [CYP]
221
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Texas Instruments TMS320C6670 Quick Start Manual (2 pages)
Evaluation Module
Brand:
Texas Instruments
| Category:
Motherboard
| Size: 0.65 MB
Texas Instruments TMS320C6670 Quick Start Manual (2 pages)
Evaluation Module
Brand:
Texas Instruments
| Category:
Control Unit
| Size: 0.83 MB
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