Clock; Odule; Av.link Antiglitch Filter; Format Description Of Transmitted Frames - Analog Devices Advantiv ADV7604 Hardware Manual

13.4 Clock Generator Module
This module is used to generate the AV.link process clock based on the Xtal clock. The clock divider
register is used to control the clock divider factor. The output clock frequency is given by
15.
Equation 15: Input-Output Relationship for AV.link Clock Divider
AVL_CLOCK_DIVIDER[7:0], Clock Divider Value , AVLINK Map, Address 0x57, [7:0]
Function
AVL_CLOCK_DI
VIDER[7:0]
xxxxxxxx
00111110

13.5 AV.link Antiglitch Filter

A programmable glitch filter is used to neglect spurious or very short width bits. This module is used
to ignore short glitches on the control line. Bits are ignored with timing less than the threshold set in
the AVL_GLITCH_FILTER_CTRL register. The threshold is expected to be small in reality for a
clock of 1 MHz, and the exact value can be determined through practical examination.
AVL_GLITCH_FILTER_CTRL[5:0], Glitch Filter Control , AVLINK Map, Address 0x28, [5:0]
Function
AVL_GLITCH_FI
LTER_CTRL[5:0]
xxxxxx
000111

13.6 Format Description of Transmitted Frames

The host specifies the mode of the frame to be transmitted in the AVL_FRAME_MODE register, the
header in the AVL_FRAME_HEADER register, and the transmitted message payload registers (refer
to Table 80). The bits that are transmitted for all three modes are described below.
Note that for all three modes, the transmission of the start sequence bits is handled by the AV.link
controller itself, the microcontroller does not have to specify this separately.
Rev. F August 2010
=
f
_
AVLink

CLOCK

Description
AV.link clock is the Xtal clock divided by value set in this register
Default value
Description
Pulse within number of Xtal clock cycles that must be recognized as a
glitch
Default value

Table 84: Start Sequence Table

Mode
1
2
3
f
xtal
_ _
AVL CLOCK DIVIDER
Start Sequence
(binary format)
1b0 (ESC)
2b10
3b110
370
ADV7604
Equation
+
1