Secondary Power-Down Controls - Analog Devices Advantiv ADV7604 Hardware Manual

• Configuring the ADV7604 in power-save mode (by setting PWR_SAVE_MODE) or power-
down mode (by setting POWER_DOWN) effectively powers down the same sections. The
only difference between power-save mode and power-down mode is the activity signal that
can be output on SYNC_OUT/INT2 when the ADV7604 is in power-save mode (refer to
Section 3.2).
PWR_SAVE_MODE, IO Map, Address 0x0C, [3]
Function
PWR_SAVE_
MODE
0
1
3.2.3

Secondary Power-Down Controls

The following controls allow various sections of the ADV7604 to be powered down.
CP_PWRDN, IO Map, Address 0x0C, [2]
For a power-sensitive application, it is possible to stop the clock to the CP to reduce power. The
CP_PWRDN bit enables this CP power-save mode. The Data Preprocessor (DPP), VDP, and HDMI
blocks are not affected by this power-save mode.
Function
CP_PWRDN
0
1
XTAL_PDN, IO Map, Address 0x0B, [0]
XTAL_PDN allows the user to power down the XTAL clock in the following sections:
• STDI blocks
• SSPD blocks
• Free run synchronization generation block
2
• I
C sequencer block, which is used for the configuration of the gain, clamp, and offset
• CP section
• DPP section
The XTAL clock is also provided to the HDCP engine in the HDMI receiver. The XTAL clock
within these sections is not affected by XTAL_PDN.
Function
XTAL_PDN
0
1
Rev. F August 2010
Description
Chip operational
ADV7604 in power-save mode
Description
CP operational
CP in power-save mode.
Description
Powers up XTAL to the digital core
Powers down XTAL to the digital core
33
ADV7604