Synchronization Output Signals Polarity - Analog Devices Advantiv ADV7604 Hardware Manual

3.5.9

Synchronization Output Signals Polarity

INV_LLC_POL, IO Map, Address 0x06, [0]
The polarity of the pixel clock that leaves the ADV7604 via the LLC pin can be inverted using the
INV_LLC_POL bit. Note that this inversion affects only the LLC output pin. The other output pins
are not affected by INV_LLC_POL.
Changing the polarity of the LLC clock output may be necessary in order to meet the setup and hold
time expectations of the chips processing the output data of the ADV7604. It is expected that these
parameters must be met regardless of the type of video data (SD, PR, HD, or GR) that is
transmitted. Therefore,
Function
INV_LLC_POL
0
1
The HSync, VSync, DE, FIELD, and SYNC_OUT output synchronization signals can be inverted via
the following control bits:
• INV_HS_POL
• INV_VS_POL
• INV_F_POL
• INV_SYNC_OUT_POL
The synchronization path is shown in
different sections of the path is the following:
• Section 1: The SSPD channel 1 receives the following signals from the AFE and HDMI
sections:
HS/CS
VS
• Section 2: The SSPD channel 2 receives the following signals from the AFE and HDMI
sections:
HS/CS
VS
• Section 3: The SSPD channel 1 outputs the following signals to the CP core:
HS with negative polarity
VS with negative polarity
• Section 4: The SSPD channel 2 outputs the following signals to the CP core:
HS with negative polarity
VS with negative polarity
Rev. F August 2010
INV_LLC_POL was designed to be mode independent.
Description
Inverts LLC output polarity
LLC output polarity normal (refer to the LLC timing diagram in the
ADV7604 Preliminary Datasheet)
Figure 6. The polarity of the synchronization signals at the
42
ADV7604