Interface To Dpp Section; Figure 48: Yc 4:2:2 Video Data Encapsulated In Hdmi Stream; Figure 49: Video Stream Output By Hdmi Core For Yc - Analog Devices Advantiv ADV7604 Hardware Manual

7.21 Interface to DPP Section

The video data from the HDMI section is sent to the CP section via the DPP block. The video data
output by the HDMI section is always in a 4:4:4 format with 36 bits per pixel, irrespective of the
encoding format the video data encapsulated in HDMI/DVI stream input to the HDMI section
receives (i.e. 4:2:2 vs. 4:4:4):
• If the HDMI section receives a stream with video encoded in a 4:4:4 format, it passes the
video data to the DPP section.
If the HDMI receiver receives video data with fewer than 12 bits used per channel component
(i.e. channel Y, C
zeroes padding the bit below the LSB, before being sent to the DPP section.
• If the HDMI section receives a stream with video encoded in a 4:2:2 format (refer to
48), the HDMI section upconverts the video data into a 4:4:4 format, according to the
UP_CONVERSION_MODE
(refer to Figure
• If fewer than 12 bits are used per channel component (i.e. channel Y, C
bits from the upconverted video data are left-shifted on each component channel with zeroes
padding the bit below the LSB, before being sent to the DPP section.

TMDS
Channel
Bit 3-0
0
Bit 7-4
1
Bit 7-0
2
Bit 7-0
Figure 48: YC
Component
Channel
Y
Cb
Cr

Figure 49: Video Stream Output by HDMI Core for YC

Rev. F August 2010
and C ), the valid bits are left-shifted on each component channel with
r b
bit, and passes the upconverted video data to the DPP section
49).
Y / Cb Y / Cr
0 0 1
Y bits 3-0 Y bits 3-0
0 1
Cb bits 3-0 Cr bits 3-0
0 0
Y bits 11-4
Y bits 11-4
1
0
Cr bits 11-4
Cb bits 11-4
0
0
C 4:2:2 Video Data Encapsulated in HDMI Stream
b r
Y / Cb / Cr Y / Cb
0 0 -1 0
Y
Bit 12-0 Y
0
Cb
Bit 12-0 Cb
0
Cr
Cr
Bit 12-0
-1
UP_CONVERSION_MODE = 1
Y / Cb Y
0 2 2 3
Y bits 3-0 Y bits 3-0
2 3
Cb bits 3-0 Cr bits 3-0
2 2
Y bits 11-4 Y bits 11-4
2 3
Cb bits 11-4 Cr bits 11-4
2 2
/ Cr Y / Cb / Cr Y / Cb
0 0 0 2 0 0
Y
1 2
Cb Cb
0 2
Cr Cr
0 0
181
and C
r
/ Cr Y / Cb ...
2 4 4
...
Y bits 3-0
4
...
Cb bits 3-0
4
Y bits 11-4 ...
4
Cb bits 11-4 ...
4
...
/ Cr Y / Cb / Cr
2 2 0 4 2
...
Y Y
3 4
Cb ...
2 4
Cr ...
2 2
C 4:2:2 Input and
b r
ADV7604
Figure
), the valid
b