Table 28: Isrc2 Packet Registers - Analog Devices Advantiv ADV7604 Hardware Manual

InfoFrame
Map Address
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
1
s
A defined by the HDMI 1.3 specifications
The ISRC1 packet registers are considered valid if
ISRC1_PCKT_RAW, IO Map, Address 0x60, [6]
ISRC1_PCKT_RAW
a packet detection flag reset condition.
Function
ISRC1_PCKT_RAW
0
1
InfoFrame
Map Address
0xF5
0xF6
0xF7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
Rev. F August 2010
R/W Register Name
R ISRC1_PB_0_17
R ISRC1_PB_0_18
R ISRC1_PB_0_19
R ISRC1_PB_0_20
R ISRC1_PB_0_21
R ISRC1_PB_0_22
R ISRC1_PB_0_23
R ISRC1_PB_0_24
R ISRC1_PB_0_25
R ISRC1_PB_0_26
R ISRC1_PB_0_27
R ISRC1_PB_0_28
indicates if an ISRC1 packet was received. This bit is also reset to 0 following
Description
No ISRC1 packet received
ISRC1 packet received

Table 28: ISRC2 Packet Registers

R/W Register Name
R/W ISRC2_PACKET_ID
R ISRC2_HEADER1
R ISRC2_HEADER2
R ISRC2_PB_0_1
R ISRC2_PB_0_2
R ISRC2_PB_0_3
R ISRC2_PB_0_4
R ISRC2_PB_0_5
R ISRC2_PB_0_6
R ISRC2_PB_0_7
R ISRC2_PB_0_8
R ISRC2_PB_0_9
R ISRC2_PB_0_10
R ISRC2_PB_0_11
R ISRC2_PB_0_12
R ISRC2_PB_0_13
R ISRC2_PB_0_14
Packet Byte No.
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
ISRC1_PCKT_RAW
Packet Byte No.
Packet Type Value
HB1
HB2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
169
ADV7604
1
is set to 1.
1