Sync Stripper Slice Level; Tri 1-8 Input Control; Description - Analog Devices Advantiv ADV7604 Hardware Manual

SYNC2_ FILTER_SEL[1:0], Selects the clamp Filter characteristic on Sync Stripper 2, AFE
Map, Address 0x15, [1:0]
Function
SYNC2_FILTER_SEL
[1:0]
00
01
10
11

6.5.2 Sync Stripper Slice Level

A comparator stage is located after the filter stage. This has programmable thresholds that offer the
user various slice levels that determine the presence of a valid synchronization pulse. The register
SLICE_LEVEL[4:0] is a 5-bit register that sets up slice levels for both Sync Stripper 1 and Sync
Stripper 2.
SLICE_LEVEL[4:0], Selects the Slice level in the two sync strippers, AFE Map, Address 0x16,
[4:0]
Function
SLICE_LEVEL[4:0]
00000
~ ~ ~ ~ ~ ~ ~
11000
~ ~ ~ ~ ~ ~ ~
11111
6.6

TRI 1-8 Input Control

6.6.1 Description

Several video connectors and cables have signals that are structured as three-level signals. These
include the European SCART connector, which has two such signals; and the Japanese D-connector,
which has three. These signals convey a lot of information about the parameters of the signal being
sent. In order for the ADV7604 to use this information, it must slice the voltage levels appearing on
TRI1 to TRI8.
On the ADV7604, the following eight pins are capable of slicing a trilevel signal:
TRI1
•
TRI2
•
TRI3
•
TRI4
•
TRI5
•
TRI6
•
HS_IN2/TRI7
•
VS_IN2/TRI8
•
Rev. F August 2010
Description
No filter
Synchronization pulse width > 250 ns
Synchronization pulse width > 1 µs
Synchronization pulse width > 2.5 µs
Description
Highest slice level
Lowest slice level
74
Clamp at 300 mV.
Slice at 600 mV - ((slice_level + 1) *
9.375 mV)
ADV7604