Tmds Measurement; Tmds Measurement After Tmds Pll - Analog Devices Advantiv ADV7604 Hardware Manual

CLOCK_TERMC_DISABLE, Terminations Control for Port C, HDMI Map, Address 0x01, [5]
Function
CLOCK_TERMC_DISAB
LE
0
1
CLOCK_TERMD_DISABLE, Terminations Control for Port D, HDMI Map, Address 0x01, [6]
Function
CLOCK_TERMD_DISAB
LE
0
1

7.10 TMDS Measurement

The ADV7604 contains logic that measures the frequency of the video pixel clock transmitted on the
TMDS clock channel. The TMDS frequency can be read back via the
TMDSFREQ_RAW registers.

7.10.1 TMDS Measurement after TMDS PLL

The TMDSFREQ and
circuit located after the TMDS PLL. The TMDS PLL must, therefore, be locked to the incoming
TMDS clock in order for the
measurement. The TMDS frequency can be obtained using
Equation 2: TMDS Frequency in MHz (Measured After TMDS PLL)
Notes:
•
Equation 2 is valid only if
external crystal used.
• The TMDS PLL lock status can be monitored via VIDEO_PLL_LCK_RAW.
shows the algorithm that can be implemented on an external controller to monitor the TMDS
clock frequency.
• The
VIDEO_PLL_LCK_RAW
the HDMI port selected via HDMI_PORT_SELECT.
• The
NEW_TMDS_FRQ_RAW
selected HDMI port changes by a programmable threshold (refer to
Rev. F August 2010
Description
If TERM_ AUTO = 0, enables clock, channel 0, channel 1, and
channel 2 terminations on port C
If TERM_ AUTO = 0, disables clock, channel 0, channel 1, and
channel 2 terminations on port C
Description
If TERM_ AUTO = 0, enables clock, channel 0, channel 1, and
channel 2 terminations on port D
If TERM_ AUTO = 0, disables clock, channel 0, channel 1, and
channel 2 terminations on port D
TMDSFREQ_FRAC
TMDSFREQ and
=
F TMDSFREQ
TMDS
XTAL_FREQ_SEL[1:0]
flag should be considered valid if a TMDS clock is input on
flag can be used to monitor if the TMDS frequency on the
measurements are provided by a clock measurement
TMDSFREQ_FRAC
Equation
_ FRAC
TMDSFREQ
+
4
is set according to the value of the
112
TMDSFREQ and
registers to return a valid
2.
Figure 30
Figure 30).
ADV7604