Basic Control - Enabling/Disabling Esdp Mode - Analog Devices Advantiv ADV7604 Hardware Manual

Control
VS_V_END_E_ADJ[5:0]
DE_V_BEG_O_ADJ[5:0]
DE_V_BEG_E_ADJ[5 :0]
DE_V_END_O_ADJ[5 :0] 0xAE[5:0]
DE_V_END_E_ADJ[5 :0] 0xAF[5:0]
All the above controls (with the exception of HS_WIDTH) are signed twos complement adjustments
that allow signals to be delayed or advanced compared with their nominal positions.
It is strongly recommended that the vertical timing control signals used to trigger the vertical timing
of the backend chip (depends on the backend chip, usually VSync signal or F/V bit of SAV/EAV
codes) are all programmed to positive values of 4 or higher. Otherwise, the robustness of the vertical
timing will be compromised for nonstandard input signals. Horizontal timing adjustments can safely
be programmed with positive or negative values.
9.9 Basic Control – Enabling/Disabling ESDP Mode
ESDP operation is only available for SD and ED component video input modes (480i, 576i, 480p,
and 576p) with embedded synchronization.
To enable ESDP mode:
• Program
PRIM_MODE[3:0]
• Enable the ESDP. This is done by programming with the following setting:
ESDP_MODE = 1
• Force ESDP 480i mode (for example, 480i):
ESDP Map, Address 0x00 = 06
• Set medium PLL speed
ESDP Map, Address 0x67 = 99
• Set ESDP Map, Address 0x79 = 0xF1 (VSync processor optimization)
• Disable the voltage clamp and enable the current clamp with the following settings:
VOLTAGE_CLAMP_EN
CURRENT_CLAMP_EN = 1
• Program the additional registers recommended by ADI for this mode, such as:
CP Map, 0x6C = 0x00 (manual clamp offset)
CP Map, 0x73 = 0xF2 (CP gain)
CP Map, 0x74 = 0x08 (CP gain)
CP Map, 0x75 = 0x82 (CP gain)
CP Map, 0x76 = 0x20 (CP gain)
To disable ESDP mode and use standard CP mode:
• Program
PRIM_MODE[3:0]
• Disable ESDP by setting ESDP_MODE to 0. This is done by programming with the
following setting: ESDP_MODE = 0
• Enable voltage clamps by setting
Rev. F August 2010
ESDP Map Address
0xAB[5:0]
0xAC[5:0]
0xAD[5:0]
and VID_STD[5:0]
= 0
and VID_STD[5:0]
VOLTAGE_CLAMP_EN
223
Adjusts
VSync end position for even field
DE start position for odd field
DE start position for even field
DE end position for odd field
DE end position for even field
as normal for the selected input format
as normal for the selected input format
to 1
ADV7604