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Table 89: HDMI Interrupts in IO Map Categorized into Three Groups
Bit Position
Register
Address
0x61
0x66
0x6B
0x70
0x75
0x7A
0x7F
0x84
*For these status bits to be valid register IO map, address 0x65 bit 7 must be set to 1
14.1.5.1 Group 1 HDMI Interrupts
The interrupts listed in
that is:
• COMP mode
(PRIM_MODE[3:0]
• GR mode
(PRIM_MODE[3:0]
• HDMI mode
(PRIM_MODE[3:0]
Interrupts
TMDS_CLK_A_ST
TMDS_CLK_B_ST
TMDS_CLK_C_ST
14.1.5.2 Group 2 HDMI Interrupts
The interrupts listed in
• The ADV7604 is configured in HMDI mode. This condition applies to the three interrupts
shown in
Table 91.
• There is TMDS activity on the selected HDMI port. This condition only applies to
VIDEO_PLL_LCK_ST.
Interrupts
INTERNAL_MUTE_ST
VIDEO_PLL_LCK_ST
DE_REGEN_LCK_ST
V_LOCKED_ST
Rev. F August 2010
7
6
5
3
3
3
3
2
3
3
3
2
-
-
-
3
3
3
3
N/A
N/A
3
3
2
-
-
-
Table 90
are valid irrespective of the mode the ADV7604 is configured in,
set to 0x01)
set to 0x10)
set to values 0x05 or 0x06)
Table 90: HDMI Interrupts Group 1
Table 91
are valid on the following conditions:
Table 91: HDMI Interrupts Group 2
4
3
3
3
3
3*
3*
3
1
1
1
N/A
N/A
N/A
3
3
3
3
3
3
3
3*
3
3
3
3
IO Map Location
0x6B[4]
0x6B[3]
0x6B[2]
IO Map Location
0x66[6]
0x6B[5]
0x6B[6]
0x6B[7]
377
ADV7604
2
1
0
3
3
3
3
1
3
N/A
3
3
3
3
3
3
3
3
3
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