Table 1: Pin Function Descriptions.........................................................................................................................................................................................18

Table 2: Pin Checker Values Corresponding to Output Pins .................................................................................................................................................47

Table 3: Primary Mode and Video Standard Selection ..........................................................................................................................................................49

Table 4: V_FREQ[2:0] Description ........................................................................................................................................................................................53

Table 5: Recommended Settings for HDMI Inputs ................................................................................................................................................................55

Table 6: Sub Functions of OP_FORMAT_SEL[7:0] .............................................................................................................................................................58

Table 7: OP_FORMAT_SEL[7:0] Modes..............................................................................................................................................................................59

Table 8: ADC Input Muxing ...................................................................................................................................................................................................67

Table 9: Manual Input Muxing ...............................................................................................................................................................................................69

Table 10: Manual Synchronization Muxing Steps..................................................................................................................................................................72

Table 11: D-Terminal Connector Characteristics (Trilevel) ..................................................................................................................................................75

Table 12: D-Terminal Connector Characteristics (Bilevel)....................................................................................................................................................75

Table 13: SCART Pin 16 ........................................................................................................................................................................................................75

Table 14: SCART Pin 8 ..........................................................................................................................................................................................................75

Table 15: Anti Alias Filter Frequency Characteristics ..........................................................................................................................................................88

Table 16: Selectable Coast Conditions .................................................................................................................................................................................133

Table 17: I

S/SPDIF Interface Description...........................................................................................................................................................................140

Table 18: DSD Interface Description....................................................................................................................................................................................141

Table 19: HBR Interface Description ...................................................................................................................................................................................143

Table 20: Selectable Mute Conditions ..................................................................................................................................................................................147

Table 21: AVI InfoFrame Registers......................................................................................................................................................................................160

Table 22: Audio InfoFrame Registers...................................................................................................................................................................................162

Table 23: SPD InfoFrame Registers .....................................................................................................................................................................................163

Table 24: MPEG InfoFrame Registers..................................................................................................................................................................................165

Table 25: VS InfoFrame Registers........................................................................................................................................................................................166

Table 26: ACP Packet Registers ...........................................................................................................................................................................................167

Table 27: ISRC1 Packet Registers ........................................................................................................................................................................................168

Table 28: ISRC2 Packet Registers ........................................................................................................................................................................................169

Table 29: Gamut Metadata Packet Registers ........................................................................................................................................................................170

Table 30: KSV List Registers Location ................................................................................................................................................................................178

Table 31: Registers Location for SHA-1 Hash Value V' .....................................................................................................................................................180

Table 32: HDMI Flags in IO Map Register 0x60 .................................................................................................................................................................184

Table 33: HDMI Flags in IO Map Register 0x65 .................................................................................................................................................................184

Table 34: HDMI Flags in IO Map Register 0x6A ................................................................................................................................................................185

Table 35: HDMI Flags in IO Map Register 0x6F.................................................................................................................................................................185

Table 36: HDMI Flags in IO Map Register 0x74 .................................................................................................................................................................185

Table 37: HDMI Flags in IO Map Register 0x79 .................................................................................................................................................................186

Table 38: HDMI Flags in IO Map Register 0x7E.................................................................................................................................................................187

Table 39: HDMI Flags in IO Map Register 0x83 .................................................................................................................................................................187

Table 40: HDMI Flags in HDMI Map ..................................................................................................................................................................................187

Table 41: DPP Filter Auto Selection.....................................................................................................................................................................................191

Table 42: Coefficients of 19-Tap Decimation Filter on Channel A .....................................................................................................................................195

Table 43: Coefficients of 19-Tap Decimation Filters on Channels B and C........................................................................................................................196

Table 44: Automatic Input Color Space Selection ...............................................................................................................................................................205

Table 45: Automatic CSC Selection .....................................................................................................................................................................................206

Table 46: CSC Configuration for All CSC Modes Reported by CSC_COEFF_SEL_RB ..................................................................................................207

Table 47: CSC Coefficients...................................................................................................................................................................................................212

Table 48: Synchronization Timing Adjustment Controls.....................................................................................................................................................222

Table 49: ESDP Setup Examples..........................................................................................................................................................................................225

Table 50. Input Ranges for HDMI Modes ............................................................................................................................................................................231

Table 51: OP_656_RANGE Description for HDMI Receiver Input Mode .........................................................................................................................239

Table 52: OP_656_RANGE Description for Analog Front End Input Mode ......................................................................................................................239

Table 53: Settings Required to Support Extended Range Video Input ................................................................................................................................245

Table 54: STDI Readback Values for SD, PR, and HD .......................................................................................................................................................275

Table 55: STDI Results for Graphics Standards...................................................................................................................................................................275

Table 56: CP Synchronization Signal Output Pins...............................................................................................................................................................278

Table 57: HS Default Timing................................................................................................................................................................................................279

Table 58: HS Default Timing (Continued 1) ........................................................................................................................................................................280

Table 59: HS Default Timing (Continued 2) ........................................................................................................................................................................280

Table 60: HS Default Timing (Continued 3) ........................................................................................................................................................................280

Table 61: VS Default Timing................................................................................................................................................................................................283

Table 62: FIELD Default Timing .........................................................................................................................................................................................285

Table 63: Default Color Output Values (CP) .......................................................................................................................................................................304

Table 64: ADV7604 External Clock and Clamp Modes ......................................................................................................................................................315

Table 65: Delay Clock Cycles for Various Operation Modes..............................................................................................................................................321

Table 66: VBI Data Standards ..............................................................................................................................................................................................323

Table 67: Default Standards on Lines for Supported Interlaced and Progressive Standards...............................................................................................323

Table 68: Details of Manual Line Programming Registers ..................................................................................................................................................324

Table 69: Details of Full Field/Frame Programming Registers............................................................................................................................................326

Table 70: Error Bits in Dehammed Output Byte ..................................................................................................................................................................328

Table 71: WST Packet Description.......................................................................................................................................................................................328

Table 72: Ancillary Data in Nibble Output Format ..............................................................................................................................................................334

403

Rev. F August 2010

Table of Contents