Analog Devices Advantiv ADV7604 Hardware Manual page 254

10.7.3.1 Signals Routing to Synchronization Channels
The ADV7604 has two synchronization channels. Each channel consists of one SSPD and one STDI
section. When an HDMI input is applied, the HDMI core will generate HSync, VSync, and DE
signals and supply them as input to the each synchronization channel shown in
from the HDMI block is denoted as HDMI_HS, and VSync from the HDMI block is denoted as
HDMI_VS. DE from the HDMI block is not shown in
core without any processing when an HDMI input is selected. As well as the HDMI sync signals,
external CSync or HSync and VSync signals applied to the pins are provided as inputs to the HSync
and VSync muxes.
Two muxes are used to select HS_1 and HS_2 from the three possible HSync signals. Similarly, two
muxes are used to select VS_1 and VS_2 from the three possible VS signals. These muxes are
controlled by SYNC_CH1_HS_SEL[1:0], SYNC_CH1_VS_SEL[1:0], SYNC_CH2_HS_SEL[1:0],
and SYNC_CH2_VS_SEL[1:0]. The outputs of these four muxes, as well as the internal
EMB_SYNC_1 and EMB_SYNC_2 signals from the sync slicers (as described in Section 10.7.2) are
passed to a clock registering and deglitch block.
SYNC_CH1_HS_SEL[1:0] , Channel 1 HSync Select, IO Map, Address 0x07, [5:4]
Function
SYNC_CH1_HS_SEL
[1:0]
00
01
10
11
SYNC_CH1_VS_SEL[1:0] , Channel 1 VSync Select, IO Map, Address 0x07, [3:2]
Function
SYNC_CH1_VS_SEL
[1:0]
00
01
10
11
SYNC_CH2_HS_SEL[1:0] , Channel 2 HSync Select, IO Map, Address 0x08, [5:4]
Function
SYNC_CH2_HS_SEL
[1:0]
00
01
10
11
Rev. F August 2010
Description
HS_IN1 or HS from HDMI set to channel 1 based on primary mode
set in PRIM_MODE[3:0]
HS_IN1
HS_IN2
HSync from HDMI source
Description
VS_IN1 or VS from HDMI set to channel 1 based on primary mode
set in PRIM_MODE[3:0]
VS_IN1
VS_IN2
VSync from HDMI source
Description
HS_IN2
HS_IN1
Reserved
HSync from HDMI source
254
Figure 82 as it is passed directly to the CP
ADV7604
Figure 82. HSync