Analog Devices AD9883A Specification Sheet
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Analog Devices AD9883A Specification Sheet

Analog Devices AD9883A Specification Sheet

110 msps/140 msps analog interface for flat panel displays
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GENERAL DESCRIPTION
The AD9883A is a complete 8-bit, 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9883A includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and HSYNC and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883A's on-chip PLL generates a pixel clock from
HSYNC and COAST inputs. Pixel clock output frequencies
110 MSPS/140 MSPS Analog Interface for
R
G
B
AIN
HSYNC
COAST
CLAMP
FILT
SCL
SDA
range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p
typical at 140 MSPS. When the COAST signal is presented,
the PLL maintains its output frequency in the absence of
HSYNC. A sampling phase adjustment is provided. Data,
HSYNC and Clock output phase relationships are maintained.
The AD9883A also offers full sync processing for composite
sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This interface is fully pro-
grammable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883A is
provided in a space-saving 80-lead LQFP surface mount plastic
package and is specified over the 0°C to 70°C temperature range.

Flat Panel Displays

FUNCTIONAL BLOCK DIAGRAM
CLAMP
AIN
CLAMP
AIN
CLAMP
SYNC
PROCESSING
AND CLOCK
GENERATION
SERIAL REGISTER
AND
POWER MANAGEMENT
A
0
AD9883A
8
A/D
R
OUTA
8
A/D
G
OUTA
8
A/D
B
OUTA
MIDSCV
DTACK
HSOUT
VSOUT
SOGOUT
REF
REF
BYPASS
AD9883A

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  • Page 1: Flat Panel Displays

    GENERAL DESCRIPTION The AD9883A is a complete 8-bit, 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 × 1024 at 75 Hz).
  • Page 2 AD9883A–SPECIFICATIONS Analog Interface = 3.3 V, V Parameter Temp Level RESOLUTION DC ACCURACY Differential Nonlinearity 25°C Full Integral Nonlinearity 25°C Full No Missing Codes Full ANALOG INPUT Input Voltage Range Minimum Full Maximum Full Gain Tempco 25°C Input Bias Current 25°C...

  • Page 3: Digital Outputs

    VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693. DATACK Load = 15 pF, Data Load = 5 pF. Specifications subject to change without notice. Test AD9883AKST-110 – 0.1 Binary 16.5 AD9883A AD9883AKST-140 Unit – 0.1 Binary 3.15 16.5 °C/W...

  • Page 4: Absolute Maximum Ratings

    ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9883A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
  • Page 5 71 70 69 68 67 66 65 64 63 62 61 PIN 1 IDENTIFIER AD9883A TOP VIEW (Not to Scale) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Table I.
  • Page 6 Hsync input. See the Sync Processing Block Diagram (Figure 12) to view how this pin is connected. (Note: Besides slicing off SOG, the output from this pin gets no other additional processing on the AD9883A. Vsync separation is performed via the sync separator.)
  • Page 7 Clock Generator Power Supply The most sensitive portion of the AD9883A is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide “quiet,” noise-free power to these pins.
  • Page 8 CLAMP pin at the appropriate time (with External Clamp = 1). The polarity of this signal is set by the Clamp Polarity bit. A simpler method of clamp timing employs the AD9883A internal clamp timing generator. The Clamp Placement register is pro- grammed with the number of pixel times that should pass after the trailing edge of HSYNC before clamping starts.
  • Page 9 Considerable care has been taken in the design of the AD9883A’s clock generation circuit to minimize jitter. As indicated in Fig- ure 5, the clock jitter of the AD9883A is less than 5% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible.
  • Page 10 HSYNC and COAST, a value of “1” is active high. Power Management The AD9883A uses the activity detect circuits, the active inter- face bits in the serial bus, the active interface override bits, and the power-down bit to determine the correct power state. There are three power states, full-power, seek mode, and power-down.
  • Page 11 There is a pipeline in the AD9883A, which must be flushed before valid data becomes available. This means four data sets are presented before valid data is available.
  • Page 12 AD9883A HSYNC PxCK 5-PIPE DELAY ADCCK DATACK OUTA HSOUT HSYNC PxCK 5-PIPE DELAY ADCCK DATACK OUTA OUTA HSOUT VARIABLE DURATION...
  • Page 13 2-Wire Serial Register Map The AD9883A is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to write and read the Control Registers through the 2-line serial interface port. Write and...
  • Page 14 AD9883A Write and Read or Default Address Read Only Bits Value 10111 00100000 00000000 00000000 Table VI. Control Register Map (continued) Register Name Function Bit 7 – Clamp Function. Chooses between HSYNC for Clamp signal or another external signal to be used for clamping.
  • Page 15 Address Read Only Bits Value NOTE The AD9883A only updates the PLL divide ratio when the LSBs are written to (register 02h). TWO-WIRE SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION 7–0 Chip Revision An 8-bit register which represents the silicon revision.
  • Page 16 The leading edge of the Hsync output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9883A then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the Hsync output, which is also phase adjusted.
  • Page 17 Vsync input pin or the output from the sync separator needs to be made (Reg- ister 0E, Bits 1, 0). Table XIX. Power-Down Settings Select Result Coast Input Pin Vsync (See above Text) AD9883A...
  • Page 18 AD9883A 4 Coast Input Polarity Override This register is used to override the internal circuitry that determines the polarity of the coast signal going into the PLL. Table XX. Coast Input Polarity Override Settings Override Bit Result Coast Polarity Determined by Chip Coast Polarity Determined by User The default for coast polarity override is 0.
  • Page 19 This bit reports the status of the coast input polarity detection circuit. It can be used to determine the polarity of the coast input. The detection circuit’s location is shown in the Sync Processing Block Diagram (Figure 12). AD9883A Function No Activity Detected Activity Detected...
  • Page 20 2-WIRE SERIAL CONTROL PORT A 2-wire serial interface control interface is provided. Up to four AD9883A devices may be connected to the 2-wire serial inter- face, with each device having a unique address. The 2-wire serial interface comprises a clock (SCL) and a bidi- rectional data (SDA) pin.
  • Page 21 Data is read from the control registers of the AD9883A in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the slave address byte LOW to set up a sequential read operation.

  • Page 22: Pcb Layout Recommendations

    The fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the AD9883A, as that interposes resistive vias in the path.
  • Page 23 Adding a series resistor of value 50 Ω to 200 Ω can suppress reflec- tions, reduce EMI, and reduce the current spikes inside of the AD9883A. If series resistors are used, place them as close to the AD9883A pins as possible (although try not to add vias or extra length to the output trace in order to get the resistors closer).

  • Page 24: Outline Dimensions

    AD9883A 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) COPLANARITY 0.004 (0.10) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead LQFP (ST-80) 0.063 (1.60) 0.630 (16.00) BSC SQ 0.551 (14.00) BSC SQ SEATING PIN 1 PLANE TOP VIEW (PINS DOWN) 0.006 (0.15) 0.002 (0.05)

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