Figure 90: Stdi Usage Flowchart - Analog Devices Advantiv ADV7604 Hardware Manual

CH1_STDI_INTLCD , CP Map, Address 0xB1, [6]
Function
CH1_STDI_INTLCD
0
1
CH2_STDI_INTLCD , CP Map, Address 0x49, [6]
Function
CH2_STDI_INTLCD
0
1
10.8.3.3 STDI Usage
Figure 90 shows a flowchart of the intended usage of the STDI block.
Set CHX_STDI_CONT to 0
Set CHX_TRIG_STDI to 0=>1
(positive transition on bit)
to start the STDI state
machine
Rev. F August 2010
Description
Indicates a video signal on channel 1 with non interlaced timing. The
readback from this register is valid if
Indicates a signal on channel 1 with interlaced timing. The readback
from this register is valid if
Description
Indicates a video signal on channel 2 with non interlaced timing. The
readback from this register is valid if
Indicates a signal on channel 2 with interlaced timing. The readback
from this register is valid if
Continuous
No
Mode?
STDI Block
examines input
(flags this by setting
CHX_STDI_DVALID to 0)
Low
Read and test
CHX_STDI_DVALID
High
End application reads
video detection results
CHX_BL[13:0], CHX_LCVS[4:0],
CHX_LCF[10:0] and CHX_FCL[12:0]
End application determines
video standard and programs
PRIM_MODE and VID_STD
accordingly

Figure 90: STDI Usage Flowchart

CH1_STDI_DVALID
CH1_STDI_DVALID
CH2_STDI_DVALID
CH2_STDI_DVALID
Yes
STDI state machine will run
274
is high.
is high.
is high.
is high.
Set CHX_STDI_CONT to 1
continuously
Software function of system controller
Decoder hardware function
ADV7604