Figure 102: Ancillary Synchronization Information Output On Vs/Field Pin - Analog Devices Advantiv ADV7604 Hardware Manual

The SSPD decides between embedded synchronization and digital input. Refer to Section
details on the SSPD.
S S P DR e s u l t f r o m S e le c t e d S y n c C h a n n e l
S lic e d S y n c f r o m S e le c t e d C h a n n e l
V S fr o m S e le c t e d S y n c C h a n n e l
I2C Co n t r o ls
In t er n al S ig n al

Figure 102: Ancillary Synchronization Information Output on VS/FIELD Pin

DS_OUT, CP Map, Address 0x85, [0]
Function
DS_OUT
0
1
10.9.7.2 Ancillary Synchronization Signals Output on SYNC_OUT/INT2 Pin
The ancillary synchronization information on the SYNC_OUT/INT2 pin is shown in
In low power mode (that is, when
is a logic combination of all possible synchronization signals, is presented on the
SYNC_OUT/INT2 pin. The SYNC_OUT/INT2 pin can be configured to output the SYNC_OUT
signal by setting INT2_EN
activity signal, as shown, is intended to be used as a wake up signal. While it is not possible to
determine easily the type of input signal (horizontal and vertical frequency) that is connected, the
mere presence of synchronization information should be enough to trigger system operation. The
group of signals to be monitored is controlled by PWR_SAV_SOG_SEL[1:0].
The SEL_RAW_CS signal selects between the following options:
• When
SEL_RAW_CS
This HSync signal arrives from two possible sources.
Rev. F August 2010
V S E xt r a c tio n
(S yn ch r o n o us t o X ta l )
G e ne rat e V syn c
(S yn ch r o n o us t o LLC)
Description
Selects LLC synchronous VSync
Selects Xtal synchronous VSync
PWR_SAVE_MODE
to 0. This enables a dynamic power-down system to be put in place. The
is set to 0, an HSync type input is passed through to the next stage.
V S _ O U T _ S E L
F R E E _ R U N
0
0
1
1
G e nera t e Fie ld
(Syn ch r o n o us t o LLC)
V S _ O U T _ S E L
is set to 1), the SYNC_OUT signal, which
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ADV7604
10.8
D S _ O U T
1
0
0
1
0
1
Figure 103.
for
V S _ O U T