Sync Extracted By Sync Slicer Section; Figure 81: Sliced Signal Path - Analog Devices Advantiv ADV7604 Hardware Manual

10.7.2 Sync Extracted by Sync Slicer Section

The ADV7604 has two sync slicers that can slice one of the two possible embedded sync signals,
SYNC1 and SYNC 2. The sliced signals are output on the internal sliced signals
EMB_SYNC_SEL_1
sliced signals are output on the internal signals EMB_SYNC_1 and EMB_SYNC_2. These are
internal signals that are passed to the STDI/SSPD stage of sync processing (refer to Section 10.7).
The muxes are controlled by
SYNC_CH2_EMB_SYNC_SEL[1:0]. By default, both of these controls are 0b00, so EMB_SYNC_1
receives either the output of sync slicer 1 or a LO signal, depending on the selected PRIM_MODE.
EMB_SYNC_2 receives the output of sync slicer 2.
Both these signals are passed to the STDI/SSPD stage of the sync processing, discussed in
Section 10.7. Refer to Section
SYNC_CH1_EMB_SYNC_SEL[1:0] , Channel 1 Embedded Sync Selection, IO Map, Address
0x07, [1:0]
Function
SYNC_CH1_EMB_
SYNC_SEL[1:0]
00
01
10
11
Rev. F August 2010
and EMB_SYNC_SEL_2.
SYNC_CH1_EMB_SYNC_SEL[1:0]
SYNC_CH1_EMB_SYNC_SEL[1:0]
PRIM_MODE[2]
EMB_SYNC_SEL_1
EMB_SYNC_SEL_2
SYNC_CH2_EMB_SYNC_SEL[1:0]

Figure 81: Sliced Signal Path

6.5 for additional information on the sync slicers.
Description
Automatically selects EMB_SYNC_SEL_1 in ADC mode or Tie to
LO in HDMI mode. Based on Primary mode.
EMB_SYNC_SEL_1
EMB_SYNC_SEL_2
Reserved
A pair of muxes allows the user to select which
and
0
LO 1 00
01
10 EMB_SYNC_1
LO 11
00
01
10 EMB_SYNC_2
LO 11
252
ADV7604