Secondary Synchronization Signals; Ancillary Synchronization Signal Outputs - Analog Devices Advantiv ADV7604 Hardware Manual

10.9.6 Secondary Synchronization Signals

The secondary synchronization signals share their output pins with the primary ones, as shown in
Table 56. The CSync signal is a logic combination of HSync and VSync. Its polarity can be inverted
using the INV_HS_POL
The DE signal allows the ADV7604 to interface seamlessly to ICs such as DVI or HDMI
transmitters. The DE signal marks active video on all active lines and could, therefore, also be
described as an inverted blanking signal. The polarity of the DE signal can be changed by the
INV_F_POL bit.
Notes:
• The delay units are:
LLC clock cycles for HS. With nominal sampling, this is equivalent to pixels.
Video lines for VSync and FIELD.
• Synchronization information can also be passed on to downstream equipment by means of
AV codes. There is an option in the AV code generation block that uses the position of the
HS pin to trigger the insertion of SAV/EAV codes into the data stream.

10.9.7 Ancillary Synchronization Signal Outputs

The ADV7604 can provide ancillary synchronization information on the VS/FIELD and the
SYNC_OUT/INT2 output pins. The following sections describe the available signals.
10.9.7.1 Ancillary Synchronization Signals Output on VS/FIELD Pin
Figure 102 outlines the structure implemented in the ADV7604.
The DS_OUT bit enables selection between the regenerated line-locked VSync (synchronous to
LLC ) and a raw asynchronous version of the vertical synchronization. Depending on the
application and the ultimate purpose of the timing signal, both of them can have distinct advantages:
• The synchronous signals aligned with the pixel data can be captured with the LLC clock.
They accompany the data and determine the position of the vertical synchronization with
pixel accuracy. As a prerequisite, the LLC clock must be locked and this requires
PRIM_MODE[3:0], VID_STD[5:0], and other registers to be configured correctly.
• The asynchronous signals are not aligned with the video pixel data. However, they are
valid even if the LLC is not locked to input video. For a digital VS input signal, the data
path to the VS output pin is combinatorial logic. For embedded synchronization, the vertical
synchronization is extracted based on the external crystal clock. This makes both paths
independent of the status of the LLC clock. These synchronization signals can be used in a
system that chooses to implement auto detection of the input video standard downstream
with the use of a microprocessor.
Rev. F August 2010
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