Analog Devices Advantiv ADV7604 Hardware Manual page 295

1. A raw HSync signal with no polarity detection. This raw HSync signal can be passed
straight through to the RAW_SYNC pin by selecting
PWR_SAVE_MODE
2. A circuit that extracts HSync from an applied CSync signal or embedded
synchronization signal. The applied CSync signal must have impairments such as
Macrovision pseudo syncs removed.
• When SEL_RAW_CS is set to 1, a CSync signal can be passed through to the RAW_SYNC
pin. This synchronization signal can be derived from two possible sources.
1. The logic AND result of an applied HSync and VSync to give a CSync. Both HSync and
VSync are polarity corrected in order to generate a proper CSync signal.
2. A sliced embedded synchronization or CSync without polarity detection.
All input signals to this block are asynchronous in nature (not line locked) and do not follow fixed
set up and hold time specifications with respect to the LLC signal. They are based on either
combinatorial signal paths through the ADV7604 or use digital logic that is driven off the external
crystal clock. This makes them independent of the lock state of the LLC.
SEL_RAW_CS, Digital Synchronization Output Selection , IO Map, Address 0x0B, [6]
Function
SEL_RAW_CS
0
1
Rev. F August 2010
= 0.
Description
Gives raw HSync type signal through SYNC_OUT/INT2 pin if not in
power save mode
Gives raw CSync type signal through SYNC_OUT/INT2 pin if not in
power save mode
SEL_RAW_CS
295
ADV7604
= 0 and