Input Signal Detection; Hsync Separation; Vsync/Field Separation - Analog Devices Advantiv ADV7604 Hardware Manual

9.5

Input Signal Detection

The ESDP contains circuitry for identifying characteristics of the input signal. The status readback
from this circuitry are used within the device to automatically configure it optimally for each input.
The detections done include:
• Presence/absence of a video-like signal on the input (series of synchronization type shapes at
regular intervals). Optionally, the ESDP free runs the output timing/video based in the
absence of an input video signal.
• Presence/absence of head switches/HSync phase discontinuities on the input signal.
• Automatic discrimination of SD/ED input formats, if enabled.
• Automatic discrimination of 480/576 line formats, if enabled.
• Measurement of noise level of input signal in ADC codes, measured in the synchronization
tip region of the video signal and averaged over time.
9.6

HSync Separation

ESDP uses a closed loop method of line locking to the input video. A digital PLL locks on to the
synchronization shapes of the digitized Y/G input and controls the ADC sampling clock via a Direct
Digital Frequency Synthesizer (DDFS) to generate line locked samples. The loop response of this
HSync PLL varies in response to the detected input signal type, as follows:
• Fast loop response for VCR type inputs with phase discontinuities (head switches) in order to
absorb any phase steps in the video as quickly as possible.
• Slow loop response for very noisy inputs to reject noise on the input synchronizations and
provide stable timing.
• User selectable medium to slow loop response for clean inputs (low noise and without HSync
phase discontinuities), slower to minimize jitter, less slow to allow for some timing
imperfections on the input.
9.7

VSync/Field Separation

ESDP uses an algorithm for detecting VSyncs and field sequence on the input which, as well as
behaving correctly for standard 480/576 line SD/ED inputs, is also robust to many imperfections on
input signals. These include:
• Inputs with nonstandard vertical frequency (±5 Hz)
• Very noisy inputs from weak RF channels.
• Inputs with constant, but nonstandard, field/frame lengths and with regular field sequence.
• Inputs with regular frame length but unequal field lengths, such as VCR pause modes.
• Inputs with irregular field lengths and irregular field sequence, such as VCR trick modes.
A characteristic of the robust VSync/Field separation for all of the above conditions is that there is
some latency (four lines) in making the VSync/Field decision. This allows the entire VSync to be
analyzed before the timing decision is made. Therefore, by default, there is a four line delay on all
output vertical timing signals (VSync, DE, Field, V bit, and F bit of SAV/EAV codes) compared
with the specification. To maintain correct picture alignment, it is required that the backend chip
Rev. F August 2010
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ADV7604