Configuring External Clock And Clamp Mode; Table 64: Adv7604 External Clock And Clamp Modes - Analog Devices Advantiv ADV7604 Hardware Manual

10.16.3 Configuring External Clock and Clamp Mode

The following register control bits must be configured for external clock and clamp mode operation:
•
PRIM_MODE[3
•
VID_STD[5:0],
• EXT_CLAMP_DECIM_MODE[1:0], IO Map, Address 0x00[7:6]
• EXT_VCLMP_REGEN, CP Map, Address 0xC5[4]
•
EXT_VCLMP_LINE_DLY_EN,
• EXT_VCLMP_POS_EDGE_SEL, CP Map, Address 0xBF[4]
• CP_ANVC_POS_START[12:0], CP Map, Addresses 0xC6[7:0], 0xCA[7:4], 0xC9[7]
•
CP_ANVC_POS_DURATION[7:0],
• CP_DFC_POS_START[12:0], CP Map, Addresses 0xC8[7:0], 0xCA[3:0], 0xC9[6]
This section describes these register control bits.
PRIM_MODE[3:0], VID_STD[5:0],
internal parameters to enable ADV7604 to operate with external clock and clamp signals. To select
external clock and clamp mode, the user is required to program
VID_STD[5:0], as shown in
EXT_CLAMP_DECIM_MODE[1:0], IO Map, Address 0x00,[7:6]
The EXT_CLAMP_DECIM_MODE bit controls the decimation for external clamp modes in
between regeneration and nonregeneration mode.
Function
EXT_CLAMP_DE
CIM_MODE
00
01
10
11
PRIM_MODE[3:0] VID_STD[5:0]
0001
Rev. F August 2010
:0], IO Map, Address 0x01[3:0]
IO Map, Address 0x00[5:0]
CP Map, Address 0xC9[5]
and EXT_CLAMP_DECIM_MODE[1:0]
Table 64.
Description
1x1 mode
2x1 mode
4x1 mode
Reserved

Table 64: ADV7604 External Clock and Clamp Modes

EXT_CLAMP_MO
DE[1:0]
010010 00
010010 01
010010 10
011000 00
011000 01
011000 10
110010 01
110010 10
111000 01
111000 10
CP Map, Address 0xC7[7:0]
PRIM_MODE[3:0]
Mode Description
External clamp mode 1 1x1
External clamp mode 1 2x1
External clamp mode 1 4x1
External clamp mode 2 1x1
External clamp mode 2 2x1
External clamp mode 2 4x1
US-external clamp mode 1 2x1
US-external clamp mode 1 4x1
US-external clamp mode 2 2x1
US-external clamp mode 2 4x1
315
ADV7604
configure all the
and