DEEP_COLOR_MODE_USER[1:0], HDMI Map, Address 0x40, [5:4]
The value set in this register is effective when
Function
DEEP_COLOR_MODE_
USER[1:0]
00
01
10
11
Notes:
Deep color mode can be monitored via DEEP_COLOR_CHNG_RAW, which indicates if the
•
color depth of the processed HDMI stream has changed.
The ADV7604 can be configured to trigger an interrupt when the
•
DEEP_COLOR_CHNG_RAW
status
DEEP_COLOR_CHNG_ST
from 0 to 1. Refer to Section
DEEP_COLOR_CHNG_RAW, IO Map, Address 0x7E, [7]
Function
DEEP_COLOR_CHNG_
RAW
0
1
7.12 Video FIFO
The ADV7604 contains a FIFO located between the incoming TMDS data and the CP core (refer to
Figure
31). Data arriving over the HDMI link can be at 1X for non deep color mode, and 1.25X,
1.5X, or 2X for deep color modes. Data unpacking and data rate reduction must be performed on the
incoming HDMI data to provide the CP core with the correct data rate and data bit width. The video
FIFO is used to pass data safely across the clock domains.
The video FIFO also provides extreme robustness to jitter on the TMDS clock. The CP clock is
generated by a DPLL running on the incoming TMDS clock, and the CP clock normally contains less
jitter than the incoming TMDS clock. The video FIFO provides immunity to the incoming jitter and
resultant clock phase mismatch between the CP clock and the TMDS clock.
The video FIFO is designed to operate completely autonomously. It automatically resynchronizes the
read and write pointers if they are about to point to the same location. However, it is also possible for
the user to observe and control the FIFO operation with a number of FIFO status and control
registers, as described in
Rev. F August 2010
Description
Color depth is 24 bits per pixel
Color depth is 30 bits per pixel
Color depth is 36 bits per pixel
Color depth is 48 bits per pixel (not supported)
bit changes from 0 to 1. In that configuration, the interrupt
indicates that
14
for additional information on the configuration of interrupts.
Description
Color depth has not changed
Color depth has changed. DEEP_COLOR_CHNG_RAW is reset
to 0 by setting DEEP_COLOR_CHNG_CLR (IO Map, Address
0x80[7]) to 1.
Figure
31.
OVERRIDE_DEEP_COLOR_MODE
DEEP_COLOR_CHNG_RAW
116
ADV7604
is set to 1.
has changed
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