Analog Devices Advantiv ADV7604 Hardware Manual page 330

BIPHASE_DECOD_DISABLE , VDP Map, Address 0x61, [0]
There is a biphase decoder in the VDP that is a post processor on the decoded data and is used only
for WSS and VPS. If biphase decoder is disabled, the raw elements of the biphase decoded data are
given out in the data. For WSS, the biphase decoded results are available through the I
registers; however, the raw elements are available through the ancillary stream only.
Function
BIPHASE_DECOD_DISABLE
0
1
VDP_WSS_BIPHASE_ERROR_COUNT[3:0] , VDP Map, Address 0x46, [3:0]
VDP_VPS_BIPHASE_ERROR_COUNT[7:0] , VDP Map, Address 0x54, [7:0]
In the biphase decoder, each bit is represented by a positive or a negative transition. If these
transitions are not detected by the VDP during bit time, this represents an error. The number of errors
detected while decoding WSS and VPS are counted and stored in the WSS and VPS biphase error
count registers respectively.
Function
VDP_WSS_BIPHASE_ERROR_
COUNT[3:0]
xxxx
Function
VDP_WPS_BIPHASE_ERROR_
COUNT[7:0]
xxxx xxxx
VITC_STRIP_SYNC_DISABLE , VDP Map, Address 0x61, [1]
VITC has a synchronization sequence of 10 between each data byte. The VDP can decode and strip
these synchronizations from the data stream to give out only the data bytes.
Function
VITC_STRIP_SYNC_DISABLE
0
1
Rev. F August 2010
Description
Enables biphase decoding of incoming VPS or WSS signal
Disables biphase decoding of incoming VPS or WSS signal
Description
Indicates the number of errors encountered while decoding
the biphase WSS standard
Description
Indicates the number of errors encountered while decoding
the biphase VPS standard
Description
Enables stripping of synchronizations (10) from the VITC
input signal
Disables stripping of synchronizations (10) from the VITC
input signal
330
ADV7604
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