Analog Devices Advantiv ADV7604 Hardware Manual page 402

ADV7604
Figure 74 AV Code Output Options (CP).............................................................................................................................................................................244
Figure 75: CP DATA Path Channel A (Y) for Analog Mode ..............................................................................................................................................246
Figure 76: CP Data Path Channel B/C (UV) for Analog Mode ...........................................................................................................................................247
Figure 77: CP Data Path Channel A/B/C (RGB) for Analog Mode.....................................................................................................................................248
Figure 78: CP Data Path Channel A (Y) for HDMI Mode...................................................................................................................................................249
Figure 79: CP Data Path Channel B/C for HDMI Mode......................................................................................................................................................250
Figure 80: Syncs Extracted by ESDP Section ......................................................................................................................................................................251
Figure 81: Sliced Signal Path ...............................................................................................................................................................................................252
Figure 82: External/HDMI Syncs Routing to CP Section ...................................................................................................................................................253
Figure 83: Final Sync Muxing Stage ...................................................................................................................................................................................257
Figure 84: SSPD Auto Detection Flowchart.........................................................................................................................................................................260
Figure 85: SSPD VSync and HSync Monitoring Operation.................................................................................................................................................266
Figure 86: STDI Horizontal Locking Operation...................................................................................................................................................................271
Figure 87: STDI HSync Monitoring Operation ....................................................................................................................................................................271
Figure 88: STDI Vertical Locking Operation .......................................................................................................................................................................272
Figure 89: STDI VSync Monitoring Operation ....................................................................................................................................................................272
Figure 90: STDI Usage Flowchart ........................................................................................................................................................................................274
Figure 91: STDI Values for GR Mode (Plot) .......................................................................................................................................................................276
Figure 92: ADV7604 Synchronization Signal Processing Flow Diagram ...........................................................................................................................277
Figure 93: Synchronization Repositioning and Displayed Area ..........................................................................................................................................278
Figure 94: HS Timing............................................................................................................................................................................................................281
Figure 95: 525i VS Timing ...................................................................................................................................................................................................287
Figure 96: 625i VS Timing ...................................................................................................................................................................................................288
Figure 97: 525p VS Timing ..................................................................................................................................................................................................289
Figure 98: 625p VS Timing ..................................................................................................................................................................................................289
Figure 99: 720p VS Timing .................................................................................................................................................................................................290
Figure 100: 1080i VS Timing ...............................................................................................................................................................................................291
Figure 101: 1080p VS Timing ..............................................................................................................................................................................................292
Figure 102: Ancillary Synchronization Information Output on VS/FIELD Pin ..................................................................................................................294
Figure 103: Ancillary Synchronization Information Output on SYNC_OUT/INT2 Pin.....................................................................................................296
Figure 104: Synchronization Lock Robustness Measurement .............................................................................................................................................297
Figure 105: Free Run Field Length Selection for Channel 1 and Channel 2 .......................................................................................................................303
Figure 106: System Delay for External Clock and Clamp Mode.........................................................................................................................................313
Figure 107: External Clock and Clamp Mode Block Diagram ............................................................................................................................................314
Figure 108: Regenerated Clamp Pulse Position Control ......................................................................................................................................................318
Figure 109: System Delay in ADV7604 ...............................................................................................................................................................................320
Figure 110: WSS (625i) Waveform ......................................................................................................................................................................................344
Figure 111: CGMS (525i) Waveform ...................................................................................................................................................................................345
Figure 112: CCAP Waveform and Decoded Data Correlation ............................................................................................................................................346
Figure 113: VITC Waveform and Decoded Data Correlation..............................................................................................................................................347
Figure 114: CEC Block Diagram..........................................................................................................................................................................................351
Figure 115: State Machine of CEC Transmitter ...................................................................................................................................................................355
Figure 116: State Machine of CEC Receiver........................................................................................................................................................................358
Figure 117: CEC Module Initialization ................................................................................................................................................................................360
Figure 118: Using CEC Module as Initiator .........................................................................................................................................................................360
Figure 119: Using CEC Module as Follower .......................................................................................................................................................................361
Figure 120: AV.link Block Diagram.....................................................................................................................................................................................362
Figure 121: AV.link Command Block ..................................................................................................................................................................................364
Figure 122: Transmitter Core State Machine........................................................................................................................................................................366
Figure 123: AV.link Receiver State Machine.......................................................................................................................................................................369
Figure 124: Mode 1 Frame Format .......................................................................................................................................................................................371
Figure 125: Mode 2 Frame Format .......................................................................................................................................................................................371
Figure 126: Mode 3 Frame Format .......................................................................................................................................................................................371
Figure 127: Pseudo C Code for Mode Detection..................................................................................................................................................................373
Figure 128: Pseudo C Code for ESC/DIR Bit Validation ....................................................................................................................................................373
Figure 129: Processing Trilevel Interrupts............................................................................................................................................................................381
2
Figure 130: ADV7604 Register Map Access through Main I C Port ..................................................................................................................................383
Figure 131: Bus Data Transfer ..............................................................................................................................................................................................385
Figure 132: Read and Write Sequence..................................................................................................................................................................................385
Figure 133: Internal E-EDID and HDCP Registers Access from Port A.............................................................................................................................386
Figure 134: Internal E-EDID and HDCP Registers Access from Port B .............................................................................................................................387
Figure 135: Internal E-EDID and HDCP Registers Access from Port C .............................................................................................................................387
Figure 136: Internal E-EDID and HDCP Registers Access from Port D.............................................................................................................................388
Figure 137: Recommended Power Supply Decoupling........................................................................................................................................................390
Figure 138: Crystal Circuit....................................................................................................................................................................................................391
Figure 139: BGA Package.....................................................................................................................................................................................................400
402
Rev. F August 2010