List Of Figures - Analog Devices Advantiv ADV7604 Hardware Manual

List of Figures

Figure 1: Field Description Format.........................................................................................................................................................................................11
Figure 2: Functional Block Diagram ......................................................................................................................................................................................17
Figure 3: ADV7604 Pin Configuration...................................................................................................................................................................................18
Figure 4: Using +5 V from HDMI Source to Provide Supplies in Power-down Mode 0 ......................................................................................................30
Figure 5: Hardware Configuration Recommended When PWRDNB Pin Required to Enter Power-down Mode 0.............................................................31
Figure 6: Synchronization Path ...............................................................................................................................................................................................43
Figure 7: Spreadsheet Screen Shot..........................................................................................................................................................................................57
Figure 8: Video Signal Path to ADCs .....................................................................................................................................................................................65
Figure 9: Video Input Signal Level Prior to 24 Ohm to 51 Ohm Resistor Divider ...............................................................................................................66
Figure 10: Video Input Signal Level After Voltage Clamps ..................................................................................................................................................66
Figure 11: Typical Configurations Using AIN_SEL[2:0] ......................................................................................................................................................68
Figure 12: ADV7604 AFE Functional Diagram.....................................................................................................................................................................70
Figure 13: Typical Example of Manual Synchronization Muxing.........................................................................................................................................72
Figure 14: Synchronization Stripper Circuit...........................................................................................................................................................................73
Figure 15: D-Terminal Resistor Dividers ...............................................................................................................................................................................76
Figure 16: SCART Connector Resistor Dividers....................................................................................................................................................................76
Figure 17: Trilevel Slicer ........................................................................................................................................................................................................78
Figure 18: Anti Aliasing Filters Responses ............................................................................................................................................................................89
Figure 19: Functional Block Diagram of HDMI Core ...........................................................................................................................................................90
Figure 20: SPI PROM Data Image Structure..........................................................................................................................................................................97
Figure 21: Internal EDID RAM Map.....................................................................................................................................................................................99
Figure 22: Mapping Between Internal EDID RAM and EDID Map ...................................................................................................................................100
Figure 23: Port A E-EDID Structure and Mapping ..............................................................................................................................................................101
Figure 24: Port B E-EDID Structure and Mapping for SPA Located in EDID Block 1......................................................................................................102
Figure 25: Port B E-EDID Structure and Mapping for SPA Located in EDID Block 2......................................................................................................103
Figure 26: Port B E-EDID Structure and Mapping for SPA Located in EDID Block 3......................................................................................................103
Figure 27: Low Frequency Gain Response...........................................................................................................................................................................108
Figure 28: High Frequency Gain Response ..........................................................................................................................................................................108
Figure 29: Overall Gain of Equalizer Process ......................................................................................................................................................................109
Figure 30: Monitoring TMDS Clock Frequency ..................................................................................................................................................................114
Figure 31: HDMI Video FIFO ..............................................................................................................................................................................................117
Figure 32: HDCP ROM Access After Power Up .................................................................................................................................................................123
Figure 33: HDCP ROM Access After KSV Update from the Transmitter ..........................................................................................................................123
Figure 34: Horizontal Timing Parameters ............................................................................................................................................................................127
Figure 35: Vertical Parameters for Field 0............................................................................................................................................................................129
Figure 36: Vertical Parameters for Field 1............................................................................................................................................................................130
Figure 37: Audio Processor Block Diagram .........................................................................................................................................................................131
Figure 38: Audio FIFO..........................................................................................................................................................................................................134
Figure 39: Monitoring Audio Packet Type Processed by ADV7604 ...................................................................................................................................137
Figure 40: Timing Audio Data Output via I
Figure 41: Timing Audio Data Output via I
Figure 42: Timing Audio Data Output via I
Figure 43: IEC 60958 Sub-frame Timing Diagram..............................................................................................................................................................141
Figure 44: AES3 Sub-frame Timing Diagram......................................................................................................................................................................141
Figure 45: AES3 Stream Timing Diagram ...........................................................................................................................................................................141
Figure 46: DSD Timing Diagram ........................................................................................................................................................................................142
Figure 47: Reading Valid Channel Status Flags ...................................................................................................................................................................153
Figure 48: YC C 4:2:2 Video Data Encapsulated in HDMI Stream ...................................................................................................................................181
b r
Figure 49: Video Stream Output by HDMI Core for YC
Figure 50: Video Data Output by DPP in 4:2:2 Pass Through Mode ..................................................................................................................................183
Figure 51: DPP Block Diagram ............................................................................................................................................................................................189
Figure 52: Manual and Default DCM Filter Response Selection.........................................................................................................................................192
Figure 53: DPP Predetermined Filter Responses Available in Manual Selection Mode .....................................................................................................194
Figure 54: Chroma 4x Filter Responses in Manual Selection Mode....................................................................................................................................198
Figure 55: Channel B/C Decimation by 2 for Fs = 13.5 MHz .............................................................................................................................................199
Figure 56: Default Channel B/C Decimation by 2 with DPP_CHROMA_LOW_EN = 1 for Fs = 13.5 MHz ..................................................................199
Figure 57: Default Channel A/D Decimation by 2, Channel B/C Decimation by 2 and 4 for Fs = 27 MHz .....................................................................200
Figure 58: Default Channel A/D Decimation by 2, Channel B/C Decimation by 2 and 4 with DPP_CHROMA_LOW_EN = 1 for Fs = 27 MHz.........200
Figure 59: Default Channel A/D Decimation by 4, Channel B/C Decimation by 4 and 8 for Fs = 54 MHz ......................................................................201
Figure 60: Default Channel A/D Decimation by 4, Channel B/C Decimation by 4 and 8 with DPP_CHROMA_LOW_EN = 1 for Fs = 54 MHz.........201
Figure 61: DPP/CP CSC Block Diagram..............................................................................................................................................................................202
Figure 62: Configuring DPP/CP CSC Blocks ......................................................................................................................................................................202
Figure 63: ADV7604 HDMI Auto CSC Flowchart..............................................................................................................................................................208
Figure 64: ADV7604 HDMI Auto CSC Flowchart (Case RGB) .........................................................................................................................................208
Figure 65: ADV7604 HDMI Auto CSC Flowchart (Case YCbCr-1) ..................................................................................................................................209
Figure 66: ADV7604 HDMI Auto CSC Flowchart (Case YCbCr-2) ..................................................................................................................................209
Figure 67: ADV7604 Manual RGB Range Control Flowchart for Auto CSC (Case RGB)................................................................................................210
Figure 68: Single CSC Channel ............................................................................................................................................................................................211
Figure 69: ESDP Block Diagram..........................................................................................................................................................................................220
Figure 70: Component Processor Block Diagram ................................................................................................................................................................226
Figure 71: Position of Voltage Clamp Window ...................................................................................................................................................................227
Figure 72: CP Automatic Gain Controls...............................................................................................................................................................................232
Figure 73: Channel A, B, and C Automatic Value Selection ...............................................................................................................................................241
Rev. F August 2010
2 2
S Pins in I S Mode .........................................................................................................................................140
2
S Pins in Right Justified Mode.......................................................................................................................140
2
S Pins in Left Justified Mode.........................................................................................................................140
C 4:2:2 Input and UP_CONVERSION_MODE = 1 ................................................................181
b r
401
ADV7604