Figure 93: Synchronization Repositioning And Displayed Area; Table 56: Cp Synchronization Signal Output Pins - Analog Devices Advantiv ADV7604 Hardware Manual

• DE (indicates active region) shared with the FIELD pin
Timing reference signals with shared pins are controlled via I
Pin Name Primary Signal
(Default)
HS/CS HSync out
FIELD/DE FIELD out
VS/FIELD VSync out
The user can program the primary and secondary synchronization signals, repositioning them in
order to control the display area, as shown in
positioning control is also available for the auto graphics mode. Refer to Section
details.

Figure 93: Synchronization Repositioning and Displayed Area

Rev. F August 2010

Table 56: CP Synchronization Signal Output Pins

Secondary Signal
CSync out
DE out
FIELD out
Figure
Vertical Blanking
Displayed Area
(Odd Field)
Vertical Blanking
Displayed Area
(Even Field)
Vertical Blanking
Displayed Area
(Odd Field)
2
C.
93. Note that VBI (Vertical Blanking Interval)
START_HS [9:0]
DE_H_START [9:0]
278
2
Controlled by I C Bit
HS_OUT_SEL[1:0]
F_OUT_SEL
VS_OUT_SEL
10.15 for further
HSYNC/DE SIGNAL
ADV7604