Timing Controls - Analog Devices Advantiv ADV7604 Hardware Manual

END_VS[3:0] End VS Signal , CP Map, Address 0x7F, [7:4]
This 4-bit word operates in a twos compliment mode. Shifting the trailing edge of the VSync
towards active video is achieved by selecting from the range 0x0 to 0x7. Shifting the trailing edge
of the VSync away from active video is achieved by selecting from the range 0x8 to 0xF. One LSB
increment is equivalent to 1 line shift.
Examples of how to control the end of the VS timing signal:
END_VS[3:0]
0000
0001
0011
0111
1111
1101
1000
1
VS closer to start of active video
2
VS away from start of active video
10.9.4 DE Timing Controls
DE_H_END[9:0] , CP Map, Address 0x8B[1:0], 0x8C [7:0]
This bit is used to adjust the trailing edge of the DE signal output by the CP core.
Function
DE_H_END[9:0]
0000000000
DE_H_START[9:0] , CP Map, Address 0x8B[3:2], 0x8D[7:0]
This bit is used to adjust the leading edge of the DE signal output by the CP core.
Function
DE_H_START[9:0]
0000000000
Rev. F August 2010
Hex Result
0x0 No move (default)
0x1 1 HS shift later than default
0x3 3 HS shift later than default
0x0 7 HS shift later than default
0xF 1 HS shift earlier than default
0xD 3 HS shift earlier than default
0x8 8 HS shift earlier than default
Description
Adjusts trailing edge of the DE signal output by the CP core. This
parameter is a signed number represented in a twos complement
format.
Description
Adjusts leading edge of the DE signal output by the CP core. This
parameter is a signed number represented in a twos complement
format.
1
2
284
ADV7604
Note
Minimum →
Maximum →
Minimum ←
Maximum ←