Figure 85: Sspd Vsync And Hsync Monitoring Operation - Analog Devices Advantiv ADV7604 Hardware Manual

2 22 crystal clock cycles window
Notes:
• It is possible to monitor changes in the
interrupt status SSPD_RSLT_CHNGD_CH1_ST.
• Likewise, it is possible to monitor changes in the
via the interrupt status SSPD_RSLT_CHNGD_CH2_ST.
SSPD_RSLT_CHNGD_CH1_ST , IO Map, Address 0x5C, [0]
Function
SSPD_RSLT_CHNGD_CH
1_ST
0
1
SSPD_RSLT_CHNGD_CH1_RAW , IO Map, Address 0x5B, [0]
Function
SSPD_RSLT_CHNGD_CH
1_RAW
0
1
Rev. F August 2010
Field 3 or Line 3
SSPPD monitors activity on each sync signal VS and HSover a 2

Figure 85: SSPD VSync and HSync Monitoring Operation

Description
No change in synchronization input to SSPD section of
synchronization channel 1.
Interrupt generated for SSPD_RSLT_CHNGD_CH1_ST after
SSPD_RSLT_CHNGD_CH1_RAW changed. Bit is cleared by
setting SSPD_RSLT_CHNGD_CH1_CLR (IO Map, Address
0x5D[0]) to 1.
Note that SSPD_RSLT_CHNGD_CH1_ST interrupt is enabled:
• By setting SSPD_RSLT_CHNGD_MB1 (IO Map, Address
0x5F[0]) for INT1
• By setting SSPD_RSLT_CHNGD_MB2 (IO Map, Address
0x5E[0]) for INT2
Description
No change in the synchronization input to SSPD section of
synchronization channel 1
Set to 1 for 15 crystal clock period if a change occurs in any of
these flags:
CH1_VS_ACT, CP Map, Address 0x42[6]
CH1_CUR_POL_VS, CP Map, Address 0x42[5]
CH1_HS_ACT, CP Map, Address 0x42[4]
CH1_CUR_POL_HS, CP Map, Address 0x42[3]
Field 4 or Line 4 Field 5 or Line 5
22 crystal clock cycles window
CH1_VS_ACT and
CH2_VS_ACT
266
Field 6 or Line 6 Field 7 or Line 7
2 22 crystal clock cycles window
CH1_HS_ACT flags via the
and CH2_HS_ACT
ADV7604
flags