Analog Front End; Adc Sampling Clock Adjustment; Adcs And Voltage Clamps; Adc Power Control - Analog Devices Advantiv ADV7604 Hardware Manual

6 Analog Front End

The analog front end (AFE) comprises the following:
• Three high performance 12-bit analog to digital converters (ADCs) with voltage clamps
• Twelve analog inputs and flexible multiplexing capability
• Four synchronization (SYNC1, SYNC2, SYNC3 and SYNC4) input multiplexers with
synchronization slicers and filtering
• Three variable bandwidth anti aliasing filters
• LLC-DLL (Line Locked Clock – Delay Locked Loop)
• Eight trilevel input detection blocks with associated interrupt systems
6.1

ADC Sampling Clock Adjustment

The ADC sampling clock is a line locked clock that is generated automatically by a digital encoder
synthesizer. The following controls enable the user to adjust the ADC sampling clock:
•
PLL_DIV_MAN_EN
•
PLL_DIV_RATIO
•
DLL_PHASE[4:0]
6.2

ADCs and Voltage Clamps

6.2.1 ADC Power Control

The ADV7604 has three 12-bit ADCs. It is possible to power up and power down each ADC
individually. All three ADCs are enabled when the ADV7604 powers up. Each ADC can be
controlled via the following bits:
•
PDN_ADC[0]
•
PDN_ADC[1]
•
PDN_ADC[2]

6.2.2 ADC Input Range Control

REFERENCE_TRIM[2:0], ADC Reference Trim, AFE Map, Address 0x0F, [7:5]
The full scale range of the ADCs can be adjusted by varying REFERENCE_TRIM[2:0]. The default
value for the ADC reference trim is 3b000. This must be changed to 3b100 for proper operation.
Function
REFERENCE_TRIM[2:0]
xxx
000
001
Rev. F August 2010
Description
Adjusts the ADC full-range scale
1.0 V
1.1 V
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ADV7604