Analog Devices Advantiv ADV7604 Hardware Manual page 317

EXT_VCLMP_LINE_DLY_EN, CP Map, Address 0xC9, [5]
The EXT_VCLMP_LINE_DLY_EN bit enables the user to extend the regenerated clamp
positioning in between full 1 line delay versus 1 line – clamp pulse duration.
Function
EXT_VCLMP_LIN
E_DLY_EN
0
1
Note that the EXT_VCLMP_LINE_DLY_EN bit is only available in regeneration mode and will
have an effect on both ANVC and DFC regenerated pulses.
EXT_VCLMP_POS_EDGE_SEL, CP Map, Address 0xBF, [4]
The EXT_VCLMP_POS_EDGE_SEL bit is used only for regeneration mode. It controls the clamp
pulse regeneration block to regenerate the ANVC pulse from the negative/positive clamp pulse.
Function
EXT_VCLMP_POS
_EDGE_SEL
0
1
It is possible to program the position of the analog and digital clamp operation via the following
registers:
• CP_ANVC_POS_START[12:0]
• CP_ANVC_POS_DURATION[7:0]
• CP_DFC_POS_START[12:0]
The ADV7604 has digital counters that trigger from the externally applied clamp signal, and it is
possible to program the clamp position to external clock cycle accuracy relative to these counters.
The values in Figure 108
Rev. F August 2010
Description
ANVC/DFC clamp pulse positioning limit to
1 external clock cycle < clamp pulse start < 1 line – clamp duration
ANVC/DFC positioning fully programmable with full 1 line delay
Description
Uses negative edge of external clamp pulse to regenerate ANVC pulse
Uses positive edge of external clamp pulse to regenerate ANVC pulse
can be programmed.
317
ADV7604