Analog Devices Advantiv ADV7604 Hardware Manual page 3

5 PIXEL PORT CONFIGURATION....................................................................................................................... 57
5.1 LLC C
ONTROL
5.2 CP P P
IXEL ORT
5.3 B R
US OTATION AND
5.4 P D
IXEL ATA AND
5.5 R
OUNDING AND
5.6 DDR O
UTPUT
6 ANALOG FRONT END ......................................................................................................................................... 64
6.1 ADC S
AMPLING
6.2 ADC V
S AND
6.2.1 ADC Power Control.................................................................................................................................... 64
6.2.2 ADC Input Range Control........................................................................................................................... 64
6.2.3 Clamping..................................................................................................................................................... 65
6.3 A I
NALOG NPUT
6.3.1 Analog Input Routing Recommendation ..................................................................................................... 66
6.3.2 Auto Configuration ..................................................................................................................................... 67
6.3.3 Recommended Analog Input Configurations .............................................................................................. 67
6.3.4 Manual Input Muxing ................................................................................................................................. 68
6.4 SYNC 1, SYNC 2, SYNC 3
6.4.1 Automatic Synchronization Configuration.................................................................................................. 71
6.4.2 Manual Synchronization Configuration...................................................................................................... 71
6.4.3 Manual Synchronization Application.......................................................................................................... 72
6.5 S
YNCHRONIZATION
6.5.1 Synchronization Filter Stage....................................................................................................................... 73
6.5.2 Sync Stripper Slice Level............................................................................................................................. 74
6.6 TRI 1-8 I
NPUT
6.6.1 Description.................................................................................................................................................. 74
6.6.2 D-Terminal Connector................................................................................................................................ 75
6.6.3 SCART Connector....................................................................................................................................... 75
6.6.4 TRI 1-8 Input Resistor Selection ................................................................................................................. 75
6.6.5 Trilevel Slicers ............................................................................................................................................ 77
6.6.6 Trilevel Slicer Operation ............................................................................................................................ 78
6.6.7 Bilevel/Trilevel Selection ............................................................................................................................ 79
6.6.8 Trilevel Slicer Readbacks............................................................................................................................ 81
6.6.9 Slice Level Programming............................................................................................................................ 83
6.6.10 Trilevel Interrupts .................................................................................................................................. 87
6.7 A A F
NTI LIAS
6.7.1 Description.................................................................................................................................................. 88
6.7.2 Anti Alias Filter Control ............................................................................................................................. 88
6.7.3 Anti Alias Filter Frequency Characteristics ............................................................................................... 88
7 HDMI RECEIVER ................................................................................................................................................. 90
7.1 5 V C D
ABLE ETECT
7.2 EDID/R
EPEATER
7.3 E -E
NHANCED
7.3.1 E-EDID Support for Power-down Mode 0.................................................................................................. 94
7.4 I EDID............................................................................................................................................... 99
NTERNAL
7.4.1 EDID RAM.................................................................................................................................................. 99
7.4.2 Structure of Internal E-EDID for Port A .................................................................................................. 101
7.4.3 Structure of Internal E-EDID of Ports B, C, and D .................................................................................. 102
7.5 E E-EDID........................................................................................................................................ 106
XTERNAL
7.6 T M
RANSITION
7.7 P S
ORT ELECTION
7.8 TMDS C
LOCK
7.9 C D
LOCK AND
7.10 TMDS M
EASUREMENT
7.10.1 TMDS Measurement after TMDS PLL ................................................................................................. 112
7.10.2 TMDS Measurement Prior to TMDS PLL............................................................................................ 114
7.11 D C
EEP OLOR
Rev. F August 2010
................................................................................................................................................. 57
O M ...................................................................................................................... 57
UTPUT ODES
R C
EORDERING ONTROLS
S S
YNCHRONIZATION
T D ................................................................................................................ 61
RUNCATING ATA
I AV C
NTERFACE AND ODE
C A ............................................................................................................. 64
LOCK DJUSTMENT
C ......................................................................................................................... 64
OLTAGE LAMPS
M .................................................................................................................................. 66
UXING
SYNC 4 I
AND
S ......................................................................................................................... 73
TRIPPERS
C ................................................................................................................................. 74
ONTROL
........................................................................................................................................ 88
ILTERS
.......................................................................................................................................... 90
C ........................................................................................................................ 92
ONTROLLER
D I
XTENDED ISPLAY DENTIFICATION
D
INIMIZED IFFERENTIAL
............................................................................................................................................ 110
A D ............................................................................................................ 110
CTIVITY ETECTION
T C
ATA ERMINATION ONTROL
.................................................................................................................................. 112
M S ........................................................................................................................ 115
ODE UPPORT
................................................................................................. 59
C ............................................................................... 60
IGNALS ONTROL
R .................................................................................... 63
EPETITION
C ............................................................................. 70
NPUT ONTROL
D C
ATA ONFIGURATION
S E
IGNALING QUALIZATION
.................................................................................................. 111
3
...................................................... 93
.............................................................. 106
ADV7604