Audio Control And Configuration; Figure 37: Audio Processor Block Diagram - Analog Devices Advantiv ADV7604 Hardware Manual

a Total number of lines in field 1
b Actives number of lines in field 1
c VSync front porch width in field 1. Unit is in half lines.
d VSync pulse width in field 1. Unit is in half lines.
e VSync back porch width in field 1. Unit is in half lines.
The vertical filter provides the interlaced status of the video stream. The interlaced status
INTERLACED_HDMI
INTERLACED_HDMI , HDMI Map, Address 0x0B, [4]
Function
INTERLACED_H
DMI
0
1

7.16 Audio Control and Configuration

The ADV7604 extracts L-PCM, IEC 61937 compressed, DSD or high-bit rate audio data stream
from their corresponding audio packet (i.e. audio sample, DSD or HBR packets) encapsulated inside
the HDMI data stream.
The ADV7604 also regenerates an audio master clock along with the extraction of the audio data.
The clock regeneration is performed by an integrated DPLL. The regenerated clock is used to output
audio data from the 64 stereo sample depth FIFO to the shared I
pin.
Important:
• The ADV7604 supports the extraction of stereo audio data (non compressed or compressed)
at audio sampling frequency up to 192 kHz
• The ADV7604 supports the extraction of multichannel audio data
ACRPacket
Data
TMDS Clock
Packet Process or
(Dispatch Block)
Data from HDCP
Engine/Mask
Rev. F August 2010
is valid only if the vertical filter is locked and
Description
Video stream processed by HDMI section is progressive
Video stream processed by HDMI section is interlaced
TMDSClock
N
CTS
Audio Data
To DPP
Video Data
Block

Figure 37: Audio Processor Block Diagram

2
S, SPDIF, DSD and HBR interface
MCL KOUT
Audio DPLL
12 8fs
Audio Delay
Ramped
FIFO
Line
Mute/Unmute
Chann el Status
Bits Collection
131
ADV7604
V_LOCKED_RAW is set to 1.
SPDIF /DSD0A/DST_S
I2S 0/DSD0B /HBR0
Audio
I2S1 /DSD1A/HBR1
Reconstruction
I2S 2/DSD1B/HBR2
and Serialization
I2S 3/DSD2A /HBR3
LR CLK/ DSD2B/DST_FF
SCLK/DST_CLK