Analog Devices Advantiv ADV7604 Hardware Manual
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Analog Devices Advantiv ADV7604 Hardware Manual

Component/graphics digitizer with 4:1 multiplexed hdmi receiver
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Table of Contents

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ADV7604
Component/Graphics Digitizer with 4:1
Multiplexed HDMI Receiver
Hardware Manual
Rev. F
August 2010

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Summary of Contents for Analog Devices Advantiv ADV7604

  • Page 1 ADV7604 Component/Graphics Digitizer with 4:1 Multiplexed HDMI Receiver Hardware Manual Rev. F August 2010...

  • Page 2: Table Of Contents

    ADV7604 Table of Contents INTRODUCTION TO ADV7604 HARDWARE MANUAL................. 8 ADV7604 D ........................8 OCUMENTATION ADV7604 H ..................... 8 ESCRIPTION OF ARDWARE ANUAL ............................... 8 ISCLAIMER ............................8 UMBER OTATIONS ........................9 EGISTER CCESS ONVENTIONS ........................9 CRONYMS AND BBREVIATIONS ........................
  • Page 3 ADV7604 PIXEL PORT CONFIGURATION........................57 LLC C ..............................57 ONTROL CP P ........................57 IXEL UTPUT ODES ....................59 OTATION AND EORDERING ONTROLS ................60 IXEL ATA AND YNCHRONIZATION IGNALS ONTROL ........................ 61 OUNDING AND RUNCATING DDR O AV C ..................
  • Page 4 ADV7604 7.12 FIFO ..............................116 IDEO 7.13 ............................120 IXEL EPETITION 7.14 HDCP S ............................. 121 UPPORT 7.14.1 HDCP Decryption Engine........................121 7.14.2 Internal HDCP Key OTP ROM......................122 7.14.3 HDCP Keys Access Flags ........................122 7.15 HDMI S ....................... 124 YNCHRONIZATION ARAMETERS 7.15.1...
  • Page 5 ADV7604 8.4.2 Selecting Auto or Manual CSC Conversion Mode..................204 8.4.3 Auto Color Space Conversion Matrix ....................... 205 8.4.4 HDMI Auto CSC Operation........................208 8.4.5 Manual Color Space Conversion Matrix ....................211 8.4.6 CSC in Pass-through Mode........................216 ............................217 OLOR ONTROLS ENHANCED STANDARD DEFINITION PROCESSOR.................
  • Page 6 ADV7604 10.13.2 Free Run Feature in HDMI Mode......................303 10.13.3 Free Run Default Color Output......................304 10.14 CP S ..............................307 TATUS 10.15 ..........................308 RAPHICS 10.15.1 Primary Auto Graphics Controls ......................308 10.15.2 Secondary Auto Graphics Control ....................... 309 10.15.3 Auxiliary Auto Graphics Controls......................
  • Page 7 ADV7604 13.6 ..................370 ORMAT ESCRIPTION OF RANSMITTED RAMES 13.6.1 Mode 1..............................371 13.6.2 Mode 2..............................371 13.6.3 Mode 3..............................371 13.7 ............................372 ETECTION 13.8 ESC/DIR B ..........................373 ALIDATION INTERRUPTS ............................... 374 14.1 ..............................374 NTERRUPTS 14.1.1 Interrupt Request Output Operation ....................374 14.1.2 Interrupt Drive Level..........................

  • Page 8: Introduction To Adv7604 Hardware Manual

    Component/Graphic Digitizer and quad HDMI receiver section of the ADV7604. Disclaimer The information contained in this document is proprietary of Analog Devices Inc. (ADI). This document must not be made available to anybody other than the intended recipient without the written permission of ADI.

  • Page 9: Register Access Conventions

    ADV7604 Register Access Conventions Mode Description Memory location has read and write access. Read only Memory location is read access only. A read always returns 0 unless specified otherwise. Write only Memory location is write access only. Acronyms and Abbreviations Acronym/Abbreviation Description Audio Content Protection...

  • Page 10: Field Function Description

    ADV7604 Acronym/Abbreviation Description Inter IC Sound Inter Integrated Circuit Key Selection Vector Line Locked Clock Least Significant Bit Mbps Megabit per Second MPEG Moving Picture Expert Group Millisecond Most Significant Bit One Time Programmable Receiver Slave Address Start of Active Video Standard Definition SMPTE Society of Motion Picture and Television Engineers...

  • Page 11: References

    ADV7604 Short function I2C location of the description field in big endian of the field format (MSB first, The name of the field. In this example the field is LAST last) called REFERENCE_TRIM and is 3 bit long. Detailed description REFERENCE_TRIM[2:0], ADC Reference Trim, AFE Map, Address 0x0F, [7:5] of the field ADC Reference Trim is used to adjust the ADC full range scale.
  • Page 12 ADV7604 CENELEC, EN 50157, Part 1, Domestic and similar electronic equipment interconnection requirements: AV.link CENELEC, EN 50157, Part 2-1, Domestic and similar electronic equipment interconnection requirements: AV.link CENELEC, EN 50157, Part 2-2, Domestic and similar electronic equipment interconnection requirements: AV.link CENELEC, EN 50157, Part 2-3, Domestic and similar electronic equipment interconnection requirements: AV.link Rev.

  • Page 13: Introduction

    ADV7604 2 Introduction The ADV7604 is a single chip, multiformat video decoder, and graphics digitizer with an integrated 4:1 multiplexed High-Definition Multimedia Interface (HDMI™). The ADV7604 can operate in quad HDMI and analog input mode, thus providing simultaneous HDMI and analog video sync processing. It integrates a component processor (CP), which can processes YPrPb and RGB component formats, RGB graphics and video signals from the HDMI receiver.

  • Page 14: Component Processor

    ADV7604 With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the ADV7604 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission, as specified by the HDCP v1.3b protocol.

  • Page 15: Main Features Of Adv7604

    ADV7604 Main Features of ADV7604 2.4.1 Analog Front End The analog front end functionality includes: • Four 170 MHz 12-bit ADCs enabling true 12-bit video decoding • Six analog input channel mux enabling multisource connection without the requirement of an external mux •...

  • Page 16: Rgb Graphics Processing

    ADV7604 • Support for analog component YPrPb/RGB video formats with embedded synchronization or with separate HSync, VSync, or CSync • Two any-to-any 3 × 3 CSC matrices support YCrCb to RGB and RGB to YCrCb. The second CSC supports color controls such as saturation, brightness, hue, and contrast •...

  • Page 17: Functional Block Diagram

    ADV7604 Functional Block Diagram CLAMPIN Y_MUX_OUT AIN1 AIN2 CHANNEL RAW_SYNC AIN3 ADC0 INPUT CLAMP RAW_VSYNC AIN4 MATRIX AIN5 AIN6 AIN7 CLAMP ADC1 AIN8 AIN9 BACK AIN10 CLAMP ADC2 AIN11 P0 TO P11 AIN12 P12 TO P23 EMBEDDED P24 TO P35 SYNC COMPONENT SYNC1...

  • Page 18: Pin Descriptions

    ADV7604 Pin Descriptions DGND RXD_2- RXD_1- RXD_0- RXD_C- DGND RXC_2- RXC_1- RXC_0- RXC_C- TVDD RXB_2- RXB_1- RXB_0- RXB_C- TVDD TVDD DGND RXD_5V RXD_2+ RXD_1+ RXD_0+ RXD_C+ TVDD RXC_2+ RXC_1+ RXC_0+ RXC_C+ TVDD RXB_2+ RXB_1+ RXB_0+ RXB_C+ TVDD RXA_2+ RXA_2- PWRDNB TVDD TVDD CVDD...
  • Page 19 ADV7604 Mnemonic Type Function Digital Video DE (data enable) is a signal that indicates Output active pixel data. Digital Video HS is a horizontal synchronization output Output signal in the CP and HDMI processor. Digital Video Video pixel output port. Output Digital Video Video pixel output port.
  • Page 20 ADV7604 Mnemonic Type Function DGND Ground Ground. DVDDIO Power Digital I/O supply voltage (3.3 V). Digital Video Video pixel output port. Output Digital Video Video pixel output port. Output Digital Video Video pixel output port. Output Digital Video Video pixel output port. Output Digital Video Video pixel output port.
  • Page 21 ADV7604 Mnemonic Type Function is a 3.3 V input that is 5 V tolerant. EP_MOSI Digital Input SPI master out/slave out for external EDID interface. EP_SCK Digital Output SPI clock for external EDID interface. RAW_SYNC Analog Output This pin outputs the raw-sliced, embedded CSync or raw digital HS/CS.
  • Page 22 ADV7604 Mnemonic Type Function RXC_2- HDMI Input Digital input channel 2 complement of port C in the HDMI interface. RXC_2+ HDMI Input Digital input channel 2 true of port C in the HDMI interface. TVDD Power Terminator supply voltage (3.3 V). DDCC_SCL HDMI Input HDCP slave serial clock port C.
  • Page 23 ADV7604 Mnemonic Type Function HDMI interface. DGND Ground Ground. DGND Ground Ground. DGND Ground Ground. DGND Ground Ground. DGND Ground Ground. DGND Ground Ground. DGND Ground Ground. DGND Ground Ground. DVDDIO Power Digital I/O supply voltage (3.3 V) DVDDIO Power Digital I/O supply voltage (3.3 V) Digital Video Video pixel output port...
  • Page 24 ADV7604 Mnemonic Type Function Output Digital Video Video pixel output port. Output RXB_2- HDMI Input Digital input channel 2 complement of port B in the HDMI interface. RXB_2+ HDMI Input Digital input channel 2 true of port B in the HDMI interface.
  • Page 25 ADV7604 Mnemonic Type Function is a 3.3 V input that is 5 V tolerant. AGND Ground Ground. AGND Ground Ground. AGND Ground Ground. AGND Ground Ground. RXB_C- HDMI Input Digital input clock complement of port B in the HDMI interface. RXB_C+ HDMI Input Digital input clock true of port B in the HDMI...
  • Page 26 ADV7604 Mnemonic Type Function synchronization mode. User configurable. AIN1 Analog Video Analog video input channel. Input TVDD Power Terminator supply voltage (3.3 V). TVDD Power Terminator supply voltage (3.3 V). DGND Ground Ground. TVDD Power Terminator supply voltage (3.3 V). DGND Ground Ground.
  • Page 27 ADV7604 Mnemonic Type Function TEST1 Test Connect to ground via a 10k resistor REFN Misc Analog Internal voltage reference output. AGND Ground Ground. AIN11 Analog Video Analog video input channel. Input SYNC4 Misc Analog This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode.

  • Page 28: Global Control Registers

    ADV7604 3 Global Control Registers The register control bits described in this section affect the whole chip and are not dependent on the analog digitizer mode or HDMI receiver mode for which the ADV7604 is configured. ADV7604 Revision Identification The revision can be read back via RD_INFO[7:0]. RD_INFO[7:0], IO Map, Address 0x11, [7:0] Function IDENT[7:0]...
  • Page 29 ADV7604 RXC_5V RXD_5V • DDC pads: DDCA_SCL DDCA_SDA DDCB_SCL DDCB_SDA DDCC_SCL DDCC_SDA DDCD_SCL DDCD_SDA • SPI EEPROM interface pads: EP_MOSI EP_MISO EP_CS EP_SCK • Reset pad RESETB The power-down mode 0 is initiated through either a software (I2C register) configuration or hardware configuration.

  • Page 30: Figure 4: Using +5 V From Hdmi Source To Provide Supplies In Power-Down Mode 0

    ADV7604 Power-down Pins Configuration The configuration shown in Figure 4 is required for hardware power-down with internal EDID availability. The configuration shown in Figure 5 can be implemented if there is no requirement to enter power- down mode 0 by setting the PWRDNB pin low and no requirement for an active internal EDID in a system power-down mode.

  • Page 31: Figure 5: Hardware Configuration Recommended When Pwrdnb Pin Required To Enter Power-Down Mode 0

    ADV7604 Optional ADV7604 EEPROM TV Supply 512 byte (4k bit) DVDDIO + 5 V HDMI TVDD Port A TV Supply (3.3V) + 5 V HDMI AVDD Port B CVDD DVDD PVDD + 5 V HDMI Port C PWRDNB + 5 V HDMI RXD_5V_DETECT Port D...

  • Page 32: Power-Save Mode

    ADV7604 POWER_DOWN, IO Map, Address 0x0C, [5] Function POWER_DOWN Description Power-down disabled Power-down enabled The effect of the pin PWRDNB can be disabled by setting DIS_PWRDNB to 1. When this is done, the part is in power down mode 1 if: •...

  • Page 33: Secondary Power-Down Controls

    ADV7604 • Configuring the ADV7604 in power-save mode (by setting PWR_SAVE_MODE) or power- down mode (by setting POWER_DOWN) effectively powers down the same sections. The only difference between power-save mode and power-down mode is the activity signal that can be output on SYNC_OUT/INT2 when the ADV7604 is in power-save mode (refer to Section 3.2).
  • Page 34 ADV7604 CORE_PDN, IO Map, Address 0x0B, [1] CORE_PDN allows the user to power down clocks, with the exception of the XTAL clock, in the following sections: • DPP block • CP block • ESDP block • Digital section of the HDMI block The following sections remain active when CORE_PDN is set:...

  • Page 35: Adc Power-Down Control

    ADV7604 ESDP_PDN, IO Map, Address 0x0B, [2] Function ESDP_PDN Description Powers down all the clocks running in the ESDP section Powers up all the clocks running in the ESDP section Important: For optimum power consumption saving it is advised to power up the ESDP clocks only when the part is in ESDP mode.

  • Page 36: Reset Control

    ADV7604 Reset Control The ADV7604 can be reset by a low pulse on the RESET pin (i.e. a hardware reset) with a minimum width of 5 ms. The EDID/Repeater controller in the HDMI block is not affected by this reset. It is recommended to wait 5 ms after the low pulse before an I C write is performed to the ADV7604.

  • Page 37: Global Pin Control

    ADV7604 Global Pin Control 3.5.1 Tristate Pixel Bus Drivers TRI_PIX, IO Map, Address 0x15, [1] This bit allows the user to tristate the output driver of the pixel bus. Upon setting TRI_PIX, pixel bus P[35:0] is tristated. Function TRI_PIX Description Output drivers of pixel bus P[35:0] enabled.

  • Page 38: Tristate Synchronization Output Drivers

    ADV7604 3.5.3 Tristate Synchronization Output Drivers TRI_SYNCS, IO Map, Address 0x15, [3] When TRI_SYNCS is set, the following output synchronization signals are tristated: • DE • HS/CS • VS • VS/FIELD • SYNC_OUT/INT2 The drive strength controls for these signals are provided via the DR_STR_SYNC bits.

  • Page 39: Drive Strength Selection (Data)

    ADV7604 3.5.5 Drive Strength Selection (Data) DR_STR[1:0], IO Map, Address 0x14, [5:4] It may be desirable to strengthen or weaken the drive strength of the output drivers for Electromagnetic Compatibility (EMC) and crosstalk reasons. The DR_STR[1:0] bits affect output drivers for the following output pins: •...

  • Page 40: Drive Strength Selection (Clock)

    ADV7604 3.5.6 Drive Strength Selection (Clock) DR_STR_CLK[1:0], IO Map, Address 0x14, [3:2] The DR_STR_CLK[1:0] bits allow the user to select the strength of the clock signal output driver (LLC pin). Refer to DR_STR[1:0] DR_STR_SYNC[1:0] for the drive strength control of the pixel bus, synchronization, and audio output signals.

  • Page 41: Synchronization Output Selection

    ADV7604 3.5.8 Synchronization Output Selection VS_OUT_SEL, IO Map, Address 0x06 [7] This bit selects the signal that is output on the VS/FIELD pin. Function VS_OUT_SEL Description Field signal output on VS/FIELD pin VS output on the VS/FIELD pin F_OUT_SEL, IO Map, Address 0x05, [4] This bit selects the signal that is output on the FIELD/DE pin.

  • Page 42: Synchronization Output Signals Polarity

    ADV7604 3.5.9 Synchronization Output Signals Polarity INV_LLC_POL, IO Map, Address 0x06, [0] The polarity of the pixel clock that leaves the ADV7604 via the LLC pin can be inverted using the INV_LLC_POL bit. Note that this inversion affects only the LLC output pin. The other output pins are not affected by INV_LLC_POL.

  • Page 43: Figure 6: Synchronization Path

    ADV7604 • Section 5: The CP core outputs the following signals to the output formatter section: HS with negative polarity VS with negative polarity DE with negative polarity Note that the CP core generates the DE signal for analog input. In HDMI mode, the CP core regenerates the DE signal from the DE output by the HDMI receiver section.

  • Page 44: Digital Synthesizer Controls

    ADV7604 INV_SYNC_OUT_POL, IO Map, Address 0x06, [4] INV_SYNC_OUT_POL controls the polarity of the SYNC_OUT output signal. This control is only valid when the ADV7604 outputs a CSync on the SYNC_OUT, i.e. when the part is not configured in power-save mode. Function INV_SYNC_OUT_ Description...

  • Page 45: Phase Control

    ADV7604 PLL_DIV_RATIO[12:0], IO Map, Address 0x17, [7:0], Address 0x16, [4:0] Function PLL_DIV_RATIO[ Description 12:0] xxxxxxxxxxxxx Synthesizer feedback value. PLL_MAN_VAL_EN must be set for this value to be active. In digital input mode, the pixel and audio master clocks are generated from the digital encoder synthesizer provided with the incoming TMDS clock.

  • Page 46: Cp And Hdmi Simultaneous Mode

    ADV7604 To disable the DLL on the LLC: first, bypass the DLL by setting LLC_DLL_MUX to 0. Then, disable the DLL by setting LLC_DLL_EN to 0. LLC_DLL_EN, DLL Enable, AFE Map , Address 0x13, [7] Function LLC_DLL_EN Description Powers down the DLL on LLC Powers up the DLL on LLC LLC_DLL_MUX, IO Map, Address 0x33, [6] Function...

  • Page 47: Pin Checker

    ADV7604 • The following HDMI subsections are active and functional when the ADV7604 runs in simultaneous mode: TMDS equalizer (refer to Section 7.6) TMDS clock and data terminators (refer to Section 7.9) TMDS clock detection circuitry (refer to Section 7.8) TMDS clock measurement circuitry (refer to Section 7.10) HDCP decryption engine (refer to Section 7.14.1) HDMI synchronization filters II (refer to Section 7.15)
  • Page 48 ADV7604 Pin Name Pin Checker Value P[23:16] PIN_CHECKER_VAL[7:0] P[15:08] PIN_CHECKER_VAL[7:0] P[7:0] PIN_CHECK_VAL[7:0] SYNC_OUT PIN_CHECK_VAL[7] FIELD/DE PIN_CHECKER_VAL[6] PIN_CHECK_VAL[5] PIN_CHECKER_VAL[4] Rev. F August 2010...

  • Page 49: Primary Mode And Video Standard

    ADV7604 4 Primary Mode and Video Standard Setting the primary mode and choosing a video standard are the most fundamental settings when configuring the ADV7604. There are three main modes of operation on the ADV7604. • COMP Analog-component video mode. This includes all video signals that arrive in a YPbPr (or YUV) analog format.
  • Page 50 ADV7604 PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Comment Resolution 001101 PR 2x1 625p 720 x 576 001110 PR 4x1 525p 720 x 480 001111 PR 4x1 625p 720 x 576 010000 PR 2x2 525p 1440 x 480 010001 PR 2x2 625p 1440 x 576 010010 Reserved...
  • Page 51 ADV7604 PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Comment Resolution 1024 x 768 @ 001100 XGA 1024 x 768 @ 001101 XGA 1024 x 768 @ 001110 XGA 1024 x 768 @ 001111 XGA 010000 WXGA 1280 x768 @60 With reduced 010001 WXGAR 1280 x768 @60...
  • Page 52 ADV7604 PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Comment Resolution 010011 HD 1x1 1280 x 720 010100 HD 1x1 1920 x 1080 010101 HD 1x1 1920 x 1035 010110 HD 1x1 1920 x 1080 010111 HD 1x1 1920 x 1152 011000 Reserved Reserved 011001 HD 2x1 720p 1280 x 720...

  • Page 53: Table 4: V_Freq[2:0] Description

    ADV7604 PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Comment Resolution 1111 Reserved xxxxxx Reserved Reserved V_FREQ[2:0], IO Map, Address 0x01, [6:4] These bits are used when the decoder is required to support HD standards with a refresh rate below 60 Hz.

  • Page 54: Selecting Primary Mode And Video Standard For Hdmi Modes

    ADV7604 Selecting Primary Mode and Video Standard for HDMI Modes The HDMI receiver decodes and processes any applied HDMI stream irrespective of the video resolution. However, there are many Primary Mode and Video Standards settings in order to define how the decoded video data that is routed to the DPP and CP blocks is processed. This allows for free run features and data decimation modes that some systems may require.

  • Page 55: Primary Mode And Video Standard Configuration For Hdmi Free Run

    ADV7604 Primary Mode and Video Standard Configuration for HDMI Free Run If free run is enabled in HDMI mode, PRIM_MODE[3:0] VID_STD[5:0] specify the input resolution expected by the ADV7604 (for free run mode 1) and/or the output resolution to which the ADV7604 free runs (for free run mode 0 and mode 1).
  • Page 56 ADV7604 Video ID Formats Pixel Recommended Settings if Free Recommended Settings if Codes Repetition Run is not Used Free Run is Used and (861 OR Free Run is Used and DIS_AUTOPRAM_BUFFER Specification) DIS_AUTO_PARAM_BUFF = @ 60 Hz VID_STD = 0x2 VID_STD = 0x1 25, 26 2880x480i @...

  • Page 57: Pixel Port Configuration

    ADV7604 5 Pixel Port Configuration The ADV7604 has a very flexible pixel port, which can be configured in a variety of formats to accommodate downstream ICs. The ADV7604 can provide output modes up to 36 bits. This section details the controls required to configure the ADV7604 pixel port. A spreadsheet tool, the ADV7604-output-pixel-port-mapping.xls, can generate the pinout for all combinations of pixel port configuration controls.

  • Page 58: Table 6: Sub Functions Of Op_Format_Sel[7:0]

    ADV7604 different function controls, that is, BIT_WIDTH[1:0], MODE_SEL[2:0], and OP_MODE_SEL[2:0]. (Refer to Table Table 6: Sub Functions of OP_FORMAT_SEL[7:0] OP_FORMAT_SEL[7:0] OP_MODE_SEL[2:0] MODE_SEL[2:0] BIT_WIDTH[1:0] OP_MODE_SEL[2:0], IO Map, Address 0x03, [7:5] Function OP_MODE_SEL[2:0] Description 4:2:2 SDR (pseudo DDR) 4:2:2 DDR 4:4:4 SDR 4:4:4 DDR (CLK/2) 4:2:2 SDR ADI_CM...

  • Page 59: Bus Rotation And Reordering Controls

    ADV7604 Table 7: OP_FORMAT_SEL[7:0] Modes Function OP_FORMAT_SEL[7:0] Setting 8-bit SDR 4:2:2 (pseudo DDR) mode 0 0x00 10-bit SDR 4:2:2 (pseudo DDR) mode 0 0x01 12-bit SDR 4:2:2 (pseudo DDR) mode 0 0x02 12-bit SDR 4:2:2 (pseudo DDR) mode 1 0x06 12-bit SDR 4:2:2 (pseudo DDR) mode 2 0x0A 16-bit SDR 4:2:2 mode 0...

  • Page 60: Pixel Data And Synchronization Signals Control

    ADV7604 Function OP_CH_SEL[2:0] Description Reserved Reserved PIXBUS_MSB_TO_LSB_REORDER, IO Map, Address 0x30, [4] Function PIXBUS_MSB_TO_ Description LSB_REORDER Output bus goes from MSB to LSB Output bus goes from LSB to MSB Important: Unused pins of the pixel output for any available output format are driven with a low signal.

  • Page 61: Rounding And Truncating Data

    ADV7604 Rounding and Truncating Data CP_PREC[1:0], CP Map, Address 0x77, [7:6] The CP_PREC[1:0] control is used to round and truncate data in channels A, B, and C. Function CP_PREC[1:0] Description Rounds and truncates data in channels A, B, and C to 10-bit precision Rounds and truncates data in channels A, B, and C to 12-bit precision Rounds and truncates data in channels A, B, and C to 8-bit precision Rounds and truncates data in channels A, B, and C the precision set in...
  • Page 62 ADV7604 BR_NOISE_SHAPING_GAIN [1:0], CP Map, Address 0x36, [3:2] BR_NOISE_SHAPING_GAIN control is used to set the gain applied to the noise shaping bit in mode 1. Function BR_NOISE_SHAP Description ING_GAIN 1X gain 2X gain 4X gain 8X gain TEN_TO_EIGHT_CONV, CP Map, Address 0x36, [0] TEN_TO_EIGHT_CONV control is used to configure when the data to be rounded and truncated is 10-bit and not of 12-bit data.

  • Page 63: Ddr Output Interface And Av Code Repetition

    ADV7604 DDR Output Interface and AV Code Repetition The ADV7604 allows data to be output in a DDR mode and pseudo double data rate mode. Internally, the ADV7604 produces three data streams, either R, G, and B; or Y, Cr, and Cb, depending on whether the input is RGB or is YPrPb.

  • Page 64: Analog Front End

    ADV7604 6 Analog Front End The analog front end (AFE) comprises the following: • Three high performance 12-bit analog to digital converters (ADCs) with voltage clamps • Twelve analog inputs and flexible multiplexing capability • Four synchronization (SYNC1, SYNC2, SYNC3 and SYNC4) input multiplexers with synchronization slicers and filtering •...

  • Page 65: Clamping

    ADV7604 Function REFERENCE_TRIM[2:0] Description 1.2 V 1.3 V 1.4 V (recommended setting) Reserved Reserved Reserved Important: • The part must be set as follows when REFERENCE_TRIM is set to 3b100: Set AFE Map, register 0x0C to 0x1F Set CP Map, register 0x3E[2] to 1b0 Set CP Map, register 0x40 to 0x60 •...

  • Page 66: Analog Input Muxing

    ADV7604 Y Input Signal Range Pr/Pb Input Signal Range 1.6V 1.6V Figure 9: Video Input Signal Level Prior to 24 Ohm to 51 Ohm Resistor Divider Y Signal Range Pr/Pb Signal Range 1.345 V 1.345 V ~0.5V 730mV Clamp ~0.5V 980mV Clamp 730mV...

  • Page 67: Auto Configuration

    ADV7604 6.3.2 Auto Configuration The ADV7604 has an integrated analog muxing section, which allows more than one source of video signal to be connected to the decoder. By selecting the various AIN_SEL[2:0] values, the user can direct the appropriate analog signal to a dedicated ADC. The input muxing is not dependent on PRIM_MODE[3:0] VID_STD[5:0] selection.

  • Page 68: Manual Input Muxing

    ADV7604 HS IN1 HS IN1 HS IN1 G rap hics R G B G rap hics R G B G raph ics R G B VS IN1 VS IN1 VS IN1 SYNC3 SYNC3 SYNC3 Ain7 G Ain7 G Ain7 G Ain8 Ain8 Ain 8...

  • Page 69: Table 9: Manual Input Muxing

    ADV7604 ADC_SWITCH_MAN, Manual input muxing enable, AFE Map, Address 0x02, [7] Function ADC_SWITCH_MAN Description Automatic muxing Manual muxing Once ADC_SW_MAN is set to 1, the following controls take effect. ADC0_SW_MAN[3:0], ADC0 mux configuration, AFE Map, Address 0x03, [7:4] Function ADC0_SW_MAN[3:0] Description 0000 Configures muxing for ADC0 according to...

  • Page 70: Sync 1, Sync 2, Sync 3 And Sync 4 Input Control

    ADV7604 ANALOG FRONT END (AFE) Ain4 Ain5 Ain6 Voltage ADC 0 Clamp Voltage ADC 1 Clamp Voltage ADC 2 Clamp Ain4 Voltage ADC 3 Ain5 Clamp Ain6 AIN_SEL[2:0] SYNC 2 SYNC EMB_SYNC_SEL_1 STRIPPER1 SYNC 3 Sync Channel SYNC1_FILTER_SEL[1:0] Processor emb_ sync_ sel_man [1:0]...

  • Page 71: Automatic Synchronization Configuration

    ADV7604 6.4.1 Automatic Synchronization Configuration In addition to configuring the analog input muxes, AIN_SEL[2:0] automatically controls the associated synchronization channel routing for signals with embedded synchronization, for example, Sync on Green (SOG) or Sync On Y (SOY) type signals. SOG is associated with RGB input video; SOY is associated with component YPrPb input video. Table 8 shows the routing details when AIN_SEL[2:0] is programmed.

  • Page 72: Manual Synchronization Application

    ADV7604 6.4.3 Manual Synchronization Application As can be seen in Figure 12, there are four input synchronization signals but there are only two synchronization paths. In a situation where there are more than two video sources to be monitored, EMB_SYNC_SEL_1 is the main channel to be processed and EMB_SYNC_SEL_2 is the monitoring path.

  • Page 73: Synchronization Strippers

    ADV7604 Synchronization Strippers The ADV7604 has two synchronization stripper blocks, which are placed before the synchronization processing sections, as shown in Figure 13. The purpose of a synchronization stripper is to provide a reliable synchronization signal to the STDI and SSPD circuits in the component processor so that a robust identification of the standard is made.

  • Page 74: Sync Stripper Slice Level

    ADV7604 SYNC2_ FILTER_SEL[1:0], Selects the clamp Filter characteristic on Sync Stripper 2, AFE Map, Address 0x15, [1:0] Function SYNC2_FILTER_SEL Description [1:0] No filter Synchronization pulse width > 250 ns Synchronization pulse width > 1 µs Synchronization pulse width > 2.5 µs 6.5.2 Sync Stripper Slice Level A comparator stage is located after the filter stage.

  • Page 75: D-Terminal Connector

    ADV7604 6.6.2 D-Terminal Connector Table 11 Table 12 show details of the D-terminal connector used in Japan. The signals Data Line 1, Data Line 2, and Data Line 3 are the three signals that can be applied to any of the eight TRI inputs.

  • Page 76: Figure 15: D-Terminal Resistor Dividers

    ADV7604 The recommended resistor values for voltages related to the D-terminal connector are shown in Figure 15, the values for SCART are shown in Figure Figure 15: D-Terminal Resistor Dividers Figure 16: SCART Connector Resistor Dividers Rev. F August 2010...

  • Page 77: Trilevel Slicers

    ADV7604 6.6.5 Trilevel Slicers The ADV7604 has eight trilevel slicers, as shown in Figure 17. Each trilevel slicer is capable of operating in two modes. The first mode is bilevel mode where the input signal can be sliced at a single voltage level to determine what information is being sent (refer to Table 12).

  • Page 78: Trilevel Slicer Operation

    ADV7604 Main Interrupt System AFE Interrupt System INT1, INT2 Trilevel TRI1 Slicer Trilevel TRI2 Slicer Level FB_OUT Shifter Trilevel TRI8 Slicer FB_SELECT[2:0] FB_Output_en Figure 17: Trilevel Slicer 6.6.6 Trilevel Slicer Operation Each trilevel slicer can be powered up or down. TRI1_SLICER_PWRDN, AFE Map, Address 0x1D, [6] Function TRI1_SLICER_PWRDN...

  • Page 79: Bilevel/Trilevel Selection

    ADV7604 TRI4_SLICER_PWRD, AFE Map, Address 0x20, [6] Function TRI4_SLICER_PWRDN Description Powers up the TRI4 slicer Powers down the TRI4 slicer TRI5_SLICER_PWRDN, AFE Map, Address 0x21, [6] Function TRI5_SLICER_PWRDN Description Powers up the TRI5 slicer Powers down the TRI5 slicer TRI6_SLICER_PWRDN AFE Map, Address 0x22, [6] Function TRI6_SLICER_PWRDN Description...
  • Page 80 ADV7604 TRI2_BILEVEL_SLICE_EN, AFE Map, Address 0x1E, [5] Function TRI2_BILEVEL_SLI Description CE_EN Bilevel slicing mode Trilevel slicing mode TRI3_BILEVEL_SLICE_EN, AFE Map, Address 0x1F, [5] Function TRI3_BILEVEL_SLI Description CE_EN Bilevel slicing mode Trilevel slicing mode TRI4_BILEVEL_SLICE_EN, AFE Map, Address 0x20, [5] Function TRI4_BILEVEL_SLI Description CE_EN...

  • Page 81: Trilevel Slicer Readbacks

    ADV7604 6.6.8 Trilevel Slicer Readbacks The input has two comparators on it for each trilevel slicer (refer to Figure 17). The raw results of these comparators are available via the TRIx_READBACK[1:0] registers. TRI1_READBACK[1:0], Readback for comparator results on TRI 1, AFE Map, Address 0x27, [7:6] Function TRI1_READBACK[1:...
  • Page 82 ADV7604 TRI5_READBACK[1:0], Readback for comparator results on TRI 5, AFE Map, Address 0x28, [7:6] Function TRI5_READBACK[1: Description Signal on TRI 5 is below lower slice level Signal on TRI 5 has crossed lower slice level Signal on TRI 5 has crossed upper slice level Signal on TRI 5 has crossed upper slice level TRI6_READBACK[1:0], Readback for comparator results on TRI 6, AFE Map, Address 0x28, [5:4]...

  • Page 83: Slice Level Programming

    ADV7604 6.6.9 Slice Level Programming When the slicers are in a bilevel mode of operation (refer to Section 6.6.7), the upper slicer is utilized. This offers the programmability described in Section 6.6.9.1. When any of the trilevel slicer circuits are in trilevel mode (refer to Section 6.6.7), the upper levels are sliced by the UPPER_SLICER, as described in Section 6.6.9.1.
  • Page 84 ADV7604 675 mV 825 mV 975 mV 1.125 V TRI4_UPPER_SLICE_LEVEL[2:0], Sets the upper slice level for TRI4, AFE Map, Address 0x20, [4:2] Function TRI4_UPPER_SLICE Description _LEVEL[2:0] 75 mV 225 mV 375 mV 525 mV 675 mV 825 mV 975 mV 1.125 V TRI5_UPPER_SLICE_LEVEL[2:0], Sets the upper slice level for TRI5, AFE Map, Address 0x21, [4:2]...
  • Page 85 ADV7604 TRI7_UPPER_SLICE_LEVEL[2:0], Sets the upper slice level for TRI7, AFE Map, Address 0x23, [4:2] Function TRI7_UPPER_SLICE Description _LEVEL[2:0] 75 mV 225 mV 375 mV 525 mV 675 mV 825 mV 975 mV 1.125 V TRI8_UPPER_SLICE_LEVEL[2:0], Sets the upper slice level for TRI8, AFE Map, Address 0x24, [4:2] Function TRI8_UPPER_SLICE...
  • Page 86 ADV7604 TRI2_LOWER_SLICE_LEVEL[1:0], Sets the lower slice level for TRI2 in trilevel slice mode, AFE Map, Address 0x1E, [1:0] Function TRI2_LOWER_SLIC Description E_LEVEL[1:0] 75 mV 225 mV 375 mV 525 mV TRI3_LOWER_SLICE_LEVEL[1:0], Sets the lower slice level for TRI3 in trilevel slice mode, AFE Map, Address 0x1F, [1:0] Function TRI3_LOWER_SLIC...

  • Page 87: Trilevel Interrupts

    ADV7604 TRI7_LOWER_SLICE_LEVEL[1:0], Sets the lower slice level for TRI7 in trilevel slice mode, AFE Map, Address 0x23, [1:0] Function TRI7_LOWER_SLIC Description E_LEVEL[1:0] 75 mV 225 mV 375 mV 525 mV TRI8_LOWER_SLICE_LEVEL[1:0], Sets the lower slice level for TRI8 in trilevel slice mode, AFE Map, Address 0x24, [1:0] Function TRI8_LOWER_SLIC...

  • Page 88: Anti Alias Filters

    ADV7604 Anti Alias Filters 6.7.1 Description The ADV7604 has optional anti aliasing filters on each of the three input channels. The filters are designed for SD, ED, and HD video with various bandwidths selectable via I C. These filters are most effective when ADC oversampling is selected.

  • Page 89: Figure 18: Anti Aliasing Filters Responses

    ADV7604 AA_FILT_HIG_BW[1:0] AA_FILTER_PROG_BW[1:0] Frequency (MHz) Response ADV7604 Attenuation 1000 10000 Frequency (MHz) Figure 18: Anti Aliasing Filters Responses Rev. F August 2010...

  • Page 90: Hdmi Receiver

    ADV7604 7 HDMI Receiver CEC CONTROLLER RXA_5V RXB_5V +5V Detection RXC_5V RXD_5V RXA_C RXB_C M U X RXC_C RXD_C D a ta T o D P P RXA_0 EQUAL- T o D P P RXA_1 SAMPLER IZER RXA_2 T o D P P RXB_0 EQUAL- T o D P P...
  • Page 91 ADV7604 CABLE_DET_C_RAW, 5 V Level Detect for Port C, IO Map, Address 0x6F, [2] Function CABLE_DET_C_RAW Description No 5 V level detected on port C 5 V level detected on port C CABLE_DET_D_RAW, 5 V Level Detect for Port D, IO Map, Address 0x6F, [1] Function CABLE_DET_D_RAW Description...

  • Page 92: Edid/Repeater Controller

    ADV7604 EDID/Repeater Controller The HDMI section incorporates an EDID/Repeater controller, which performs the following tasks: • Computes the E-EDID checksums for the four ports • Updates the SPA value after the E-EDID image has been loaded from the SPI EEPROM into the internal E-EDID RAM •...

  • Page 93: Enhanced-Extended Display Identification Data Configuration

    ADV7604 Enhanced-Extended Display Identification Data Configuration The ADV7604 features a RAM that can store E-EDID. This internal EDID feature can be used for the four HDMI ports A, B, C, and D. It is also possible to use an external device storage for the E-EDID data on each port, or a combination of internal EDID for some port(s) and external storage for the other port(s).

  • Page 94: E-Edid Support For Power-Down Mode 0

    ADV7604 EDID_B_ENABLE_CPU, Internal E-EDID for Port B Flag, Repeater Map, Address 0x7D, [1] Function EDID_B_ENABLE_CPU Description Internal E-EDID for port B disabled Internal E-EDID for port B enabled EDID_C_ENABLE_CPU, Internal E-EDID for Port C Flag, Repeater Map, Address 0x7D, [2] Function EDID_C_ENABLE_CPU Description...
  • Page 95 ADV7604 • The internal E-EDID is enabled for port A if an HDMI Tx tries to access the EDID through the DDC bus of port A. The EDID/Repeater controller also sets EDID_A_ENABLE_CPU to 1. • The internal E-EDID is enabled for port B if an HDMI Tx tries to access the EDID through the DDC bus of port B.
  • Page 96 ADV7604 7.3.1.3 SPI Interface The ADV7604 has a 4-pin SPI interface to load the E-EDID information from the SPI PROM: • EP_MOSI • EP_CS • EP_MISO • EP_SCK The ADV7604 SPI interface is capable of operating at up to 3MHz (SPI master max frequency). The ADV7604 uses byte-by-byte reading and page writing.

  • Page 97: Figure 20: Spi Prom Data Image Structure

    ADV7604 7.3.1.4 SPI E-EDID PROM Data Structure The ADV7604 requires data in the SPI EEPROM to be stored as shown in Figure 0x1FF SP A Location[7:0] 0x1FE Block 3 Segment 1 0x180 {Reserved [6:0], SP A Location[8]} 0x17F 0x17E Block 2 Segment 1 0x100 SP A Location[7:0]...
  • Page 98 ADV7604 7.3.1.5 SPA Configuration When the EDID/Repeater configures the internal EDID in power-down mode, it also updates the SPA registers for each port according to the SPA read from the external SPI PROM. The 2-byte SPA is located at the address specified by SPA_LOCATION in addresses 0x7F and 0xFF of the SPI PROM.

  • Page 99: Internal Edid

    ADV7604 Internal EDID 7.4.1 EDID RAM The ADV7604 features a 512 byte internal RAM dedicated to storing up to four EIA/CEA-861D compliant E-EDID blocks, which can be accessed through the DDC lines of each HDMI port (refer Figure 21). The internal E-EDID RAM is accessible through the 256 byte EDID Map via the main I C port SDA/SCL.

  • Page 100: Figure 22: Mapping Between Internal Edid Ram And Edid Map

    ADV7604 Internal EDID RAM Internal EDID RAM EDID Map 0x1FF 0x1FF 0xFF Block 3 Block 3 0x180 0x180 0x17F 0x17F Block 2 Block 2 EDID Map 0x00 0x100 0x100 0xFF 0xFF 0xFF Block 1 Block 1 0x80 0x80 0x7F 0x7F Block 0 Block 0 0x00...

  • Page 101: Structure Of Internal E-Edid For Port A

    ADV7604 7.4.2 Structure of Internal E-EDID for Port A The internal E-EDID is enabled on port A by setting EDID_A_ENABLE to 1. The structure of the internal E-EDID that is accessible on the DDC line of port A is shown in Figure The image of the internal E-EDID that is accessed on the DDC bus of port A corresponds to the data image contained in the internal EDID RAM.

  • Page 102: Structure Of Internal E-Edid Of Ports B, C, And D

    ADV7604 7.4.3 Structure of Internal E-EDID of Ports B, C, and D This section describes the structure of the internal E-EDID accessible through the DDC bus of port B. The same description applies for the structure and configuration of the internal E-EDID accessed through ports C and D.

  • Page 103: Figure 25: Port B E-Edid Structure And Mapping For Spa Located In Edid Block 2

    ADV7604 Port B E-EDID Structure 0x1FF Block 3 Checksum 0x1FF 0x1FE Internal EDID RAM Block 3 0x180 0x180 REPEATER MAP ,Reg 0x70,Reg 0x71 0x17F Block 2 Checksum 0x17F PORT_B_CHECKSUM[7:0] 0x17E 0x17E Internal EDID RAM SP A_LOCATION[8:0]+2 Block 2 REPEATER MAP ,Reg 0x70,Reg 0x71 SP A_PORT_B[15:0] SP A_LOCATION[8:0]-1 0x100...
  • Page 104 ADV7604 Notes: • When internal E-EDID is required for port B, the SPA along with its location address in the E-EDID must be programmed in the Repeater Map, registers SPA_PORT_B SPA_LOCATION respectively. • After EDID_B_ENABLE is set to 1, the ADV7604 EDID/Repeater controller computes the four checksums of the E-EDID image for port B.
  • Page 105 ADV7604 SPA_LOCATION[8:0], Source Physical Address Location, Repeater Map, Address 0x77[6], Address 0x76, [7:0] Function SPA_LOCATION[8:0] Description xxxxxxxx Location of source physical address in internal E-EDID of ports B, C, and D 00000000 Default value PORT_B_CHECKSUM[7:0], CEA Timing Extension Checksum for Port B, Repeater Map, Address 0x7A, [7:0] Function PORT_B_CHECKSUM[7...

  • Page 106: External E-Edid

    ADV7604 PORT_D_CHECKSUM[7:0], CEA Timing Extension Checksum for Port D, Repeater Map, Address 0x7C, [7:0] Function PORT_D_CHECKSUM[ Description 7:0] xxxxxxxx Checksum for E-EDID block containing SPA for port D 00000000 Default value 7.4.3.1 SPA Configuration When the EDID/Repeater configures the internal EDID in power-down mode, it also updates the SPA registers for each port according to the SPA read from the external SPI PROM.
  • Page 107 ADV7604 EQ_DYN_EN, Equalizer Dynamic Control Enable, HDMI Map, Address 0x96[0] Function EQ_DYN_EN Description Disables equalizer dynamic mode. The equalizer is configured in static mode. This configuration is not recommended. Refer to ADV7604 Software Manual for description of equalizer static controls. Enables equalizer dynamic mode.

  • Page 108: Figure 27: Low Frequency Gain Response

    ADV7604 Figure 27: Low Frequency Gain Response Figure 28: High Frequency Gain Response These two gain boost block outputs are combined together and perform an overall low frequency/high frequency compensated equalizing processing, as shown in Figure Rev. F August 2010...

  • Page 109: Figure 29: Overall Gain Of Equalizer Process

    ADV7604 Figure 29: Overall Gain of Equalizer Process EQ_DYN1_LF[7:0], EQ Dynamic LF Range1, HDMI Map, Address 0x8D, [7:0] Function EQ_DYN1_LF[7:0] Description 00011000 Default LF gain equalizer settings for dynamic mode range 1 xxxxxxxx LF gain equalizer settings for dynamic mode range 1 EQ_DYN1_HF[7:0], EQ Dynamic HF Range1, HDMI Map, Address 0x8E, [7:0] Function EQ_DYN1_HF[7:0]...

  • Page 110: Port Selection

    ADV7604 EQ_DYN3_HF[7:0], EQ Dynamic HF Range3, HDMI Map, Address 0x94, [7:0] Function EQ_DYN3_HF[7:0] Description 00101110 Default HF gain equalizer settings for dynamic mode range 3 xxxxxxxx HF gain equalizer settings for dynamic mode range 3 Port Selection HDMI_PORT_SELECT allows the selection of the active HDMI port. HDMI_PORT_SELECT, Port Selection, HDMI Map, Address 0x00, [1:0] Function HDMI_PORT_SELECT...

  • Page 111: Clock And Data Termination Control

    ADV7604 Important: • The clock detection flags is valid for a specific port as long as the TMDS clock and data termination has been enabled for that port • The clock detection flags are valid if part has been powered by setting POWER_DOWN to 0 •...

  • Page 112: Tmds Measurement

    ADV7604 CLOCK_TERMC_DISABLE, Terminations Control for Port C, HDMI Map, Address 0x01, [5] Function CLOCK_TERMC_DISAB Description If TERM_ AUTO = 0, enables clock, channel 0, channel 1, and channel 2 terminations on port C If TERM_ AUTO = 0, disables clock, channel 0, channel 1, and channel 2 terminations on port C CLOCK_TERMD_DISABLE, Terminations Control for Port D, HDMI Map, Address 0x01, [6] Function...
  • Page 113 ADV7604 TMDSFREQ[7:0] , HDMI Map, Address 0x06, [7:0] Function TMDSFREQ[7:0] Description xxxxxxxx Outputs 8-bit TMDS frequency measurement in MHz TMDSFREQ_FRAC[1:0], HDMI Map, Address 0x3B, [5:4] Function TMDSFREQ_FRA Description C[1:0] Fractional part of the TMDS frequency measurement. The unit for this measurement is ¼...

  • Page 114: Tmds Measurement Prior To Tmds Pll

    ADV7604 Figure 30: Monitoring TMDS Clock Frequency 7.10.2 TMDS Measurement Prior to TMDS PLL TMDSFREQ_RAW measurement is provided by a clock measurement circuit located before the TMDS PLL. The TMDS clock received by the ADV7604 must be stable in order for the TMDSFREQ_RAW[7:0] register to return a valid measurement.

  • Page 115: Deep Color Mode Support

    ADV7604 TMDSFREQ TMDS Equation 3: TMDS Frequency in MHz (Measured Before TMDS PLL) TMDSFREQ_RAW[7:0], HDMI Map, Address 0x52, [7:0] Function TMDSFREQ_RA Description W[7:0] xxxxxxxx Outputs 8-bit TMDS frequency measurement 7.11 Deep Color Mode Support The ADV7604 supports HDMI streams with deep color modes of 24, 30, or 36 bits per sample. The addition of a video FIFO (refer to Section 7.12) allows for the robust support of these modes.

  • Page 116: Video Fifo

    ADV7604 DEEP_COLOR_MODE_USER[1:0], HDMI Map, Address 0x40, [5:4] The value set in this register is effective when OVERRIDE_DEEP_COLOR_MODE is set to 1. Function DEEP_COLOR_MODE_ Description USER[1:0] Color depth is 24 bits per pixel Color depth is 30 bits per pixel Color depth is 36 bits per pixel Color depth is 48 bits per pixel (not supported) Notes: Deep color mode can be monitored via DEEP_COLOR_CHNG_RAW, which indicates if the...

  • Page 117: Figure 31: Hdmi Video Fifo

    ADV7604 T M D S T M D S C l o c k P L L D P L L D i v i d e r T M D S C h 0 T M D S C h a n n e l 0 T M D S S a m p l in g T M D S C h 1...
  • Page 118 ADV7604 DCFIFO_RECENTER, HDMI Map, Address 0x5A, [2] DCFIFO_RECENTER is a self clearing bit that resets the write pointer to be eight locations (maximum distance) from the read pointer. This bit does not cause DCFIFO_LOCKED to reset to zero. Function DCFIFO_RECENTER Description Does nothing Resets write pointer to be eight locations away from read pointer (self...
  • Page 119 ADV7604 DCFIFO_KILL_NOT_LOCKED, HDMI Map, Address 0x1B, [3] DCFIFO KILL_NOT_LOCKED controls whether or not the output of the FIFO is set to zero when the video PLL is unlocked. Function DCFIFO_KILL_NOT_ Description LOCKED FIFO data is output regardless of video PLL lock status FIFO output is zeroed if video PLL is unlocked DCFIFO_RESET_ON_LOCK, HDMI Map, Address 0x1B, [4] The DCFIFO can be set to recenter itself automatically when the video PLL transitions from...

  • Page 120: Pixel Repetition

    ADV7604 7.13 Pixel Repetition In HDMI mode, video formats with pixel rates below 25 Mpixels/s require pixel repetition in order to be transmitted over the TMDS link. When the ADV7604 receives this type of video format, it discards repeated pixel data automatically, based on the Pixel Repetition field available in the AVI InfoFrame.

  • Page 121: Hdcp Support

    ADV7604 DEREP_N[3:0] , HDMI Map, Address 0x41, [3:0] The value set by these bits is used to discard video pixel data and the clock when DEREP_N_OVERRIDE is set high. Function DEREP_N[3:0] Description xxxx DEREP_N+1 indicates the pixel and clock discard factor 7.14 HDCP Support 7.14.1 HDCP Decryption Engine...

  • Page 122: Internal Hdcp Key Otp Rom

    ADV7604 7.14.2 Internal HDCP Key OTP ROM The ADV7604 features an on-chip nonvolatile memory that is preprogrammed with a set of HDCP production keys. 7.14.3 HDCP Keys Access Flags The ADV7604 accesses the internal HDCP key OTP ROM (also referred to as HDCP ROM) on two different occasions: •...

  • Page 123: Figure 32: Hdcp Rom Access After Power Up

    ADV7604 Figure 32: HDCP ROM Access After Power Up Figure 33: HDCP ROM Access After KSV Update from the Transmitter Rev. F August 2010...

  • Page 124: Hdmi Synchronization Parameters

    ADV7604 Notes: • After the part has powered up, it is recommended to wait for 1 ms before checking the HDCP_KEYS_READ HDCP_KEY_ERROR flag bits. This ensures that the ADV7604 had sufficient time to access the internal HDCP ROM and set the HDCP_KEYS_READ HDCP_KEY_ERROR flag bits.

  • Page 125: Horizontal Filters And Measurements

    ADV7604 • When the HDMI synchronization filters II are used, the synchronization readback parameters are valid even while the part free runs (refer to Section 10.13) and/or when it is configured to process analog inputs in simultaneous mode (refer to Section 3.8) on the condition that the measurement filters have locked.
  • Page 126 ADV7604 Notes: • The horizontal measurements are valid only if DE_REGEN_LCK_RAW is set to 1. • The HDMI DE/HSync filter is used solely to measure the horizontal synchronization signals decoded from the HDMI stream. The HDMI DE/HSync filter is not in the main path of the synchronization processed by the part and does not delay the overall HDMI data into video data out latency.

  • Page 127: Figure 34: Horizontal Timing Parameters

    ADV7604 HSYNC_FRONT_PORCH[9:0], HSync Front Porch Width, HDMI Map, Address 0x20, [1:0]; Address 0x21, [7:0] Function HSYNC_FRONT_PORCH Description [9:0] xx xxxxxxx HSync front porch width in units of unique pixels HSYNC_PULSE_WIDTH[9:0], HSync Width, HDMI Map, Address 0x22, [1:0]; Address 0x23, [7:0] Function HSYNC_PULSE_WIDTH Description...

  • Page 128: Vertical Filters And Measurements

    ADV7604 7.15.4 Vertical Filters and Measurements The ADV7604 integrates a vertical filter that performs measurements on the VSync of the HDMI stream. These measurements are available in the HDMI Map and can be used to determine the resolution of the incoming video data. 7.15.4.1 Vertical Filter Locking Mechanism The HDMI vertical filter locks if the input VSync comes at exactly the same line count for two consecutive lines.

  • Page 129: Figure 35: Vertical Parameters For Field 0

    ADV7604 FIELD_0_HEIGHT[11:0], Active Number of Lines in Field 0, HDMI Map, Address 0x09, [3:0]; Address 0x0A, [7:0] Function FIELD_0_HEIGHT[11:0] Description xxxx xxxxxxx Active number lines in field 0 FIELD0_VS_FRONT_PORCH[12:0], VSync Front Porch Width in Field 0, HDMI Map, Address 0x2A, [4:0]; Address 0x2B, [7:0] Function FIELD0_VS_FRONT_ Description...

  • Page 130: Figure 36: Vertical Parameters For Field 1

    ADV7604 FIELD1_TOTAL_HEIGHT[12:0], Total Number of Lines in Field 1, HDMI Map, Address 0x28, [3:0]; Address 0x29, [7:0] Function FIELD1_TOTAL_HEIGHT Description [12:0] xxxxx xxxxxxx Total number of half lines in field 1 FIELD_1_HEIGHT[11:0], Active Number of Lines in Field 1, HDMI Map, Address 0x0B, [3:0]; Address 0x0C, [7:0] Function FIELD_1_HEIGHT[11:0]...

  • Page 131: Audio Control And Configuration

    ADV7604 Total number of lines in field 1 Actives number of lines in field 1 VSync front porch width in field 1. Unit is in half lines. VSync pulse width in field 1. Unit is in half lines. VSync back porch width in field 1. Unit is in half lines. The vertical filter provides the interlaced status of the video stream.

  • Page 132: Audio Dpll

    ADV7604 7.16.1 Audio DPLL The audio DPLL generates an internal audio master clock with a frequency of 128 times the audio sampling frequency, usually called fs. The audio master clock is used to clock the audio processing section. 7.16.1.1 Locking Mechanism When the upstream HDMI transmitter outputs a stable TMDS frequency and consistent audio clock regeneration values, the audio DPLL locks within two cycles of the audio master clock after the following two conditions are met:...

  • Page 133: Audio Fifo

    ADV7604 Table 16: Selectable Coast Conditions HDMI Corresponding Bit Name Description Status Registers(s) Address AC_MSK_VCLK_CH 0x13[6] When set to 1, audio DPLL coasts if VCLK_CHNG_RA TMDS clock has any irregular/missing pulses AC_MSK_VPLL_UN 0x13[5] When set to 1, audio DPLL coasts if VIDEO_PLL_LCK_ LOCK TMDS PLL unlocks...

  • Page 134: Figure 38: Audio Fifo

    ADV7604 Address Order Empty Address 63 Write Pointer Empty Address N+2 Steoro Data N-1 Address N+1 Stereo Data N-2 Address N Steoro Data 1 Address 3 Read Pointer Steoro Data 0 Address 2 Empty Address 1 Empty Address 0 Figure 38: Audio FIFO FIFO_UNDERFLO_RAW , IO Map, Address 0x79, [6] Function FIFO_UNDERFLO_RAW...

  • Page 135: Audio Packet Type Flags

    ADV7604 FIFO_NEAR_OVFL_RAW , IO Map, Address 0x79, [7] Function FIFO_NEAR_OVRFL__R Description Audio FIFO is not near overflow. Audio FIFO is near overflow as the number FIFO registers containing stereo data is greater or equal to value set in AUDIO_FIFO_ALMOST_FULL_THRESHOLD. Reset to 0 by setting FIFO_NEAR_OVRFL _CLR (IO Map, Address 0x76[7]) to 1.
  • Page 136 ADV7604 AUDIO_SAMPLE_PCKT_DET , HDMI Map, Address 0x18, [0] Function AUDIO_SAMPLE_PCKT Description _DET No L-PCM or IEC 61937 compressed audio sample packets received. L-PCM or IEC 61937 compressed audio sample packets are being received. This bit is cleared back to 0 on the leading edge of the HSync following 10 HSyncs without any audio sample packets.

  • Page 137: Audio Output Controls

    ADV7604 Figure 39: Monitoring Audio Packet Type Processed by ADV7604 7.16.4 Audio Output Controls This section describes the controls that allow the user to configure the audio outputs. It is possible to tristate the audio pins using the global controls, as described in Section 3.5.4.

  • Page 138: Mclkout Setting

    ADV7604 I2SOUTMODE[1:0], I S Output Mode Selection, HDMI Map, Address 0x03, [6:5] Function I2SOUTMODE[1:0] Description S mode. Right I S justified. Left I S justified. Raw IEC60958 mode. Outputs AES3 streams. Notes: I2SOUTMODE is effective when the ADV7604 is configured to output I2S streams or AES3 •...

  • Page 139: Audio Channel Mode

    ADV7604 7.16.6 Audio Channel Mode AUDIO_CH_MD_RAW indicates if 2-channel audio data or more than 2-channel audio data are received. AUDIO_CH_MD_RAW, IO Map, Address 0x65[4] Function AUDIO_CH_MD_RAW Description Stereo audio (may be compressed multichannel) Multichannel uncompressed audio (3 to 8 channels) Note: The AUDIO_CH_MD_RAW flag bit can be used for all the audio modes received, that is, L-...

  • Page 140: Figure 40: Timing Audio Data Output Via I

    ADV7604 • Raw SPDIF conforming to the IEC61937 specification with a sub frame format conforming to the IEC60958 specification on the SPDIF output pin when the part receives audio sample packets with non L-PCM encoded audio data (e.g. AC-3 compressed audio). The SPDIF output carries an audio stream that may be stereo or multichannel audio (e.g.

  • Page 141: Dsd Interface

    ADV7604 Figure 43: IEC 60958 Sub-frame Timing Diagram Data Validity Flag Zero Padding User Data Channel Status Block Start Flag Figure 44: AES3 Sub-frame Timing Diagram Channel A Channel B 32 Clock Slots 32 Clock Slots Frame n Frame n + 1 Figure 45: AES3 Stream Timing Diagram 7.16.8 DSD Interface The ADV7604 incorporates a 6-DSD channel interface used to output the audio stream extracted...

  • Page 142: Figure 46: Dsd Timing Diagram

    ADV7604 Notes: • DSD0A and DSD0B output must be used when in stereo mode only. DSD0A and DSD0B always carry the main 2-channel audio data. • DSD1A, DSD1B, DSD2A, and DSD2B are the surround channels. • With OVR_AUTO_MUX_DSD_OUT is set to 0, the ADV7604 will automatically switch to outputting a DSD stream when it detects DSD packets.

  • Page 143: Hbr Interface

    ADV7604 7.16.9 HBR Interface The ADV7604 can receive HBR audio stream packets. The ADV7604 outputs stream HBR data over four outputs, HBR0, HBR1, HBR2, and HBR3 in any of the following formats: • A SDPIF stream conforming to the IEC60958 specification (refer to Figure 43).

  • Page 144: Audio Muting

    ADV7604 MUX_HBR_OUT , HDMI Map, Address 0x01, [1] Function MUX_HBR_OUT Description ADV7604 outputs I S or AES3 streams according to I2SOUTMODE when it receives HBR packets. OVR_MUX_HBR must be set to 1 for MUX_HBR_OUT to be effective. ADV7604 outputs SPDIF streams when it receives HRB packets. OVR_ MUX_HBR must be set to 1 for MUX_HBR_OUT to be effective.

  • Page 145: Audio Mute Configuration

    ADV7604 7.16.10.1 Delay Line Control The audio delay line should be enabled when the ADV7604 is configured for automatic mute. The audio delay line is controlled by the MAN_AUDIO_DL_BYPASS AUDIO_DELAY_LINE_BYPASS bits. MAN_AUDIO_DL_BYPASS, HDMI Map, Address 0x0F, [7] Function MAN_AUDIO_DL_BYPASS Description Audio delay line is automatically bypassed if multichannel audio is received.
  • Page 146 ADV7604 The ADV7604 internally unmutes the audio if the following three conditions (listed in order of priority) are met: 1. Mute conditions are inactive NOT_AUTO_UNMUTE is set to 0 3. Audio unmute counter has finished counting down or is disabled Notes: •...

  • Page 147: Table 20: Selectable Mute Conditions

    ADV7604 inactive. Prevents audio from unmuting automatically after all mute conditions have become inactive. Audio can be unmuted manually if all mute conditions are inactive and NOT_AUTO_UNMUTE is set to 0 and back to 1. WAIT_UNMUTE[2:0], HDMI Map, Address 0x1A,[3:1] Function WAIT_UNMUTE[2:0] Description...
  • Page 148 ADV7604 Bit Name HDMI Description Corresponding Status Registers(s) Address MT_MSK_AVMUTE 0x16[7] Causes audio mute if AVMute is set to AV_MUTE_RAW be a general control packet MT_MSK_NOT_HDM 0x16[6] Causes audio mute if HDMI_MODE bit HDMI_MODE_RA IMODE goes low MT_MSK_NEW_CTS 0x16[5] Causes audio mute if CTS changes by CTS_PASS_THRS more than the threshold set in H_RAW...
  • Page 149 ADV7604 7.16.11.2 Audio Mute Signal The ADV7604 can output an audio mute signal that can be used to control the muting in a back end audio device processing the audio data output by the ADV7604 (e.g. DSP). The audio mute signal is output on the INT1/AMUTE pin by setting EN_MUTE_OUT_INTRQ to 1.

  • Page 150: Audio Stream With Incorrect Parity Error

    ADV7604 7.16.12 Audio Stream with Incorrect Parity Error The ADV7604 discards audio sample packets that have an incorrect parity bit. When these samples are received, the ADV7604 repeats the previous audio sample with a valid parity bit. The audio stream out of the ADV7604 can be muted further in this situation if the audio mute mask MT_MSK_PARITY_ERR is set.

  • Page 151: Monitoring Acr Parameters

    ADV7604 N, ACR N, HDMI Map, Address 0x5D, [3:0]; Address 0x5E, [7:0]; Address 0x5F, [7:0] Function Description N[19:16] Address 0x5D, [3:0] N[15:8] Address 0x5E, [7:0] N[7:0] Address 0x5F, [7:0] xxxx xxxxxxxx xxxxxxxx Readback value for N 7.17.2 Monitoring ACR Parameters The reception of ACR packets can be notified via the AUDIO_C_PCKT_RAW flag.

  • Page 152: Channel Status

    ADV7604 7.18 Channel Status Channel status bits are extracted from the HDMI audio packets of the 1 audio channel (i.e. channel 0) and stored in registers 0x36, 0x37, 0x38, 0x39, and 0x3A of the HDMI Map. 7.18.1 Validity Status Flag The channel status readback described in Section 7.18.2 to Section...

  • Page 153: Figure 47: Reading Valid Channel Status Flags

    ADV7604 Start Enable the CS_DATA_VALID_ST Initialization interrupt CS_DATA_VALID_S T set to 1 ? Check if the CS_DATA_VALID Set CS_DATA_VALID_CLR to 1 interrupt has triggered CS_DATA_VALID_R AW set to 1 Read the channel status bits in HDMI The channel status bits previously Map Reg 0x36 to 0x3A read are not valid CS_DATA_VALID_S...

  • Page 154: General Control And Mode Information

    ADV7604 7.18.2 General Control and Mode Information The general control and mode information are specified in Byte 0 of the channel status. For more information, refer to the IEC60958 standards. CS_DATA[0], Consumer/Professional Application, HDMI Map, Address 0x36, [0] Function CS_DATA[0] Description Consumer application Professional application...

  • Page 155: Category Code

    ADV7604 7.18.3 Category Code The category code is specified in Byte 1 of the channel status. The category code indicates the type of equipment that generates the digital audio interface signal. For more information, refer to the IEC60958 standards. CS_DATA[15:8], Category Code, HDMI Map, Address 0x37, [7:0] Function CS_DATA[15:8] Description...

  • Page 156: Word Length

    ADV7604 CS_DATA[29:28], Clock Accuracy, HDMI Map, Address 0x39, [5:4] Function CS_DATA[29:28] Description Level II, ±1000 ppm Level I, ±50 ppm Level III, variable pitch shifted Reserved CS_DATA[31:30], Reserved Register, HDMI Map, Address 0x39, [7:6] Function CS_DATA[31:30] Description Reserved Reset value 7.18.6 Word Length Word length information is specified in Byte 4 of the channel status bit.

  • Page 157: Channel Status Copyright Value Assertion

    ADV7604 7.18.7 Channel Status Copyright Value Assertion It is possible to overwrite the copyright value of the channel status bit that is passed to the SPDIF output. This is done via the CS_COPYRIGHT_MANUAL CS_COPYRIGHT_VALUE controls. CS_COPYRIGHT_MANUAL, HDMI Map, Address 0x50, [1] Function CS_COPYRIGHT_MANU Description...

  • Page 158: Packets And Infoframes Registers

    ADV7604 7.19 Packets and InfoFrames Registers In HDMI, auxiliary data are carried across the digital link using a series of packets. The ADV7604 detects and stores automatically the following HDMI packets: • InfoFrames • Audio Content Protection (ACP) • International Standard Recording Code (ISRC) •...
  • Page 159 ADV7604 7.19.1.2 InfoFrame Checksum Error Flags The following checksum error status registers flag when the latest received InfoFrame has a checksum error. AVI_INF_CKS_ERR_RAW, IO Map, Address 0x83, [0] Function AVI_INF_CKS_ERR_RA Description Checksum error not detected for AVI InfoFrame Checksum error detected for AVI InfoFrame AUD_INF_CKS_ERR_RAW, IO Map, Address 0x83, [1] Function AUD_INF_CKS_ERR_RA...

  • Page 160: Table 21: Avi Infoframe Registers

    ADV7604 7.19.1.3 AVI InfoFrame Registers Table 21 provides a list of readback registers for the AVI InfoFrame data. Refer to the EIA/CEA- 861D specifications for a detailed explanation of the AVI InfoFrame fields. Table 21: AVI InfoFrame Registers InfoFrame Access Register Name Byte Name Map Address...
  • Page 161 ADV7604 • AVI_INF_CKS_ERR_ST is 0. This condition applies only if ALWAYS_STORE_INF is set to 1. AVI_INFO_RAW, IO Map, Address 0x60, [0] AVI_INFO_RAW indicates if AVI InfoFrames are received. This bit is reset to 0 on the eighth leading edge of the VSync following seven VSync without any AVI InfoFrame. This bit is also reset to 0 if the part is reset or powered up, or when a TMDS clock is detected on the selected HDMI port, or when a TMDS clock with a new frequency is received, or when the part receives a DVI stream.

  • Page 162: Table 22: Audio Infoframe Registers

    ADV7604 7.19.1.4 Audio InfoFrame Registers Table 22 provides the list of readback registers available for the Audio InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the Audio InfoFrame fields. Table 22: Audio InfoFrame Registers InfoFrame Access Register Name Byte Name Map Address Type...

  • Page 163: Table 23: Spd Infoframe Registers

    ADV7604 7.19.1.5 SPD InfoFrame Registers Table 23 provides a list of readback registers available for the SPD InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the SPD InfoFrame fields. Table 23: SPD InfoFrame Registers InfoFrame Access Register Name Byte Name Map Address Type...
  • Page 164 ADV7604 • SPD_INF_CKS_ERR_ST is 0. This condition only applies if ALWAYS_STORE_INF is set to 1. SPD_INFO_RAW, IO Map, Address 0x60, [1] SPD_INFO_RAW indicates if Source Product Descriptor InfoFrames are received. This bit is also reset to 0 following a packet detection flag reset condition. Function SPD_INFO_RAW Description...

  • Page 165: Table 24: Mpeg Infoframe Registers

    ADV7604 7.19.1.6 MPEG Source InfoFrame Registers Table 24 provides a list of readback registers available for the MPEG InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the MPEG InfoFrame fields. Table 24: MPEG InfoFrame Registers InfoFrame Access Register Name Byte Name Map Address...

  • Page 166: Table 25: Vs Infoframe Registers

    ADV7604 7.19.1.7 Vendor Specific InfoFrame Registers Table 25 provides a list of readback registers available for the Vendor Specific InfoFrame. Table 25: VS InfoFrame Registers InfoFrame Register Name Byte Name Map Address 0xED VS_PACKET_ID Packet Type Value 0xEC VS_INF_VERS InfoFrame version number 0xEE VS_INF_LEN...

  • Page 167: Packet Registers

    ADV7604 VS_INFO_RAW, IO Map, Address 0x60, [4] VS_INFO_RAW indicates if Vendor Specific InfoFrames were received. This bit is reset to 0 following a packet detection flag reset condition. Function VS_INFO_RAW Description No Vendor Specific InfoFrame received Vendor Specific InfoFrame received 7.19.2 Packet Registers 7.19.2.1 ACP Packet Registers Table 26...

  • Page 168: Table 27: Isrc1 Packet Registers

    ADV7604 InfoFrame Register Name Packet Byte No. Map Address 0x89 ACP_PB_0_26 PB25 0x8A ACP_PB_0_27 PB26 0x8B ACP_PB_0_28 PB27 defined by the HDMI 1.3 specifications The ACP InfoFrame registers are considered valid if ACP_PCKT_RAW is set to 1. ACP_PCKT_RAW, IO Map, Address 0x60, [5] ACP_PCKT_RAW indicates if an ACP packet was received.

  • Page 169: Table 28: Isrc2 Packet Registers

    ADV7604 InfoFrame Register Name Packet Byte No. Map Address 0x9C ISRC1_PB_0_17 PB16 0x9D ISRC1_PB_0_18 PB17 0x9E ISRC1_PB_0_19 PB18 0x9F ISRC1_PB_0_20 PB19 0xA0 ISRC1_PB_0_21 PB20 0xA1 ISRC1_PB_0_22 PB21 0xA2 ISRC1_PB_0_23 PB22 0xA3 ISRC1_PB_0_24 PB23 0xA4 ISRC1_PB_0_25 PB24 0xA5 ISRC1_PB_0_26 PB25 0xA6 ISRC1_PB_0_27 PB26 0xA7...

  • Page 170: Table 29: Gamut Metadata Packet Registers

    ADV7604 InfoFrame Register Name Packet Byte No. Map Address 0xB6 ISRC2_PB_0_15 PB14 0xB7 ISRC2_PB_0_16 PB15 0xB8 ISRC2_PB_0_17 PB16 0xB9 ISRC2_PB_0_18 PB17 0xBA ISRC2_PB_0_19 PB18 0xBB ISRC2_PB_0_20 PB19 0xBC ISRC2_PB_0_21 PB20 0xBD ISRC2_PB_0_22 PB21 0xBE ISRC2_PB_0_23 PB22 0xBF ISRC2_PB_0_24 PB23 0xC0 ISRC2_PB_0_25 PB24 0xC1...
  • Page 171 ADV7604 HDMI Register Name Packet Byte No. Address 0x68 GAMUT_MDATA_PB_0_8 0x69 GAMUT_MDATA_PB_0_9 0x6A GAMUT_MDATA_PB_0_10 0x6B GAMUT_MDATA_PB_0_11 PB10 0x6C GAMUT_MDATA_PB_0_12 PB11 0x6D GAMUT_MDATA_PB_0_13 PB12 0x6E GAMUT_MDATA_PB_0_14 PB13 0x70 GAMUT_MDATA_PB_0_15 PB14 0x71 GAMUT_MDATA_PB_0_16 PB15 0x72 GAMUT_MDATA_PB_0_17 PB16 0x73 GAMUT_MDATA_PB_0_18 PB17 0x74 GAMUT_MDATA_PB_0_19 PB18 0x75 GAMUT_MDATA_PB_0_20...

  • Page 172: Customizing Packet/Infoframe Storage Registers

    ADV7604 7.19.3 Customizing Packet/InfoFrame Storage Registers The packet type value of each set of packet and InfoFrame registers in the InfoFrame Map is programmable. This allows the user to configure the ADV7604 to store the payload data of any packet and InfoFrames sent by the transmitter connected on the selected HDMI port. AVI_PACKET_ID , InfoFrame Map, Address 0xE0, [7:0] Function AVI_PACKET_ID...
  • Page 173 ADV7604 VS_PACKET_ID , InfoFrame Map, Address 0xEC, [7:0] Function VS_PACKET_ID Description 0x81 Default value 0xxx xxxx Packet type value of packet stored in InfoFrame Map, Address 0x45 to 0x6F 1xxx xxxx Packet type value of InfoFrame stored in InfoFrame Map, Address 0x45 to 0x6F ACP_PACKET_ID , InfoFrame Map, Address 0xF2, [7:0] Function...

  • Page 174: Repeater Support

    ADV7604 • 0x03: General Control Packet • 0x07: DSD Audio Sample Packet • 0x09: HBR Audio Stream Packet 7.20 Repeater Support The ADV7604 incorporates an EDID/Repeater controller that provides all the features required for a receiver front end of a fully HDCP 1.3 compliant repeater system. The ADV7604 has a RAM that can store up to 24 KSVs, which allows it to handle up to 24 downstream devices in repeater mode (refer to Table...

  • Page 175: Repeater Actions Required By External Controller

    ADV7604 KSV_LIST_READY, Repeater Map, Address 0x77, [7] KSV_LIST_READY bit is set by an external controller driving the ADV7604 to notify the ADV7604 on-chip EDID/Repeater controller that the KSV List registers have been updated. When KSV_LIST_READY is set to 1 after an AKSV update, the EDID/Repeater controller computes the SHA-1 hash value V’, updates the corresponding V’...
  • Page 176 ADV7604 7.20.2.2 KSV FIFO Read from HDCP Registers The KSV FIFO read at address 0x43 through the HDCP port of the selected HDMI port is dependant on the value of the REPEATER bit (i.e. BCAPS[6]): • When the REPEATER bit is set to 0, the KSV FIFO read from the HDCP port always returns •...

  • Page 177: Hdcp Registers Available In Repeater Map

    ADV7604 7.20.3 HDCP Registers Available in Repeater Map BKSV[39:0], Repeater Map, Address 0x00, [7:0], Address 0x01, [7:0], Address 0x02, [7:0], Address 0x03, [7:0], Address 0x04, [7:0] The receiver Key Selection Vector (BKSV) can be read back once the part has successfully accessed the HDCP ROM (refer to Section 7.14.2).

  • Page 178: Table 30: Ksv List Registers Location

    ADV7604 Table 30: KSV List Registers Location Register Name Register Addresses Number KSV0[39:0] 0x80[7:0]: KSV0[7:0] 0x81[7:0]: KSV0[15:8] 0x82[7:0]: KSV0[23:16] 0x83[7:0]: KSV0[31:24] 0x84[7:0]: KSV0[39:32] KSV1[39:0] 0x85[7:0]: KSV1[7:0] 0x86[7:0]: KSV1[15:8] 0x87[7:0]: KSV1[23:16] 0x88[7:0]: KSV1[31:24] 0x89[7:0]: KSV1[39:32] KSV2[39:0] 0x8A[7:0]: KSV2[7:0] 0x8B[7:0]: KSV2[15:8] 0x8C[7:0]: KSV2[23:16] 0x8D[7:0]: KSV2[31:24] 8x8E[7:0]: KSV2[39:32] KSV3[39:0]...
  • Page 179 ADV7604 Register Name Register Addresses Number 0xB0[7:0]: KSV9[31:24] 0xB1[7:0]: KSV9[39:32] KSV10[39:0] 0xB2[7:0]: KSV10[7:0] 0xB3[7:0]: KSV10[15:8] 0xB4[7:0]: KSV10[23:16] 0xB5[7:0]: KSV10[31:24] 0xB6[7:0]: KSV10[39:32] KSV11[39:0] 0xB7[7:0]: KSV11[7:0] 0xB8[7:0]: KSV11[15:8] 0xB9[7:0]: KSV11[23:16] 0xBA[7:0]: KSV11[31:24] 0xBB[7:0]: KSV11[39:32] KSV12[39:0] 0xBC[7:0]: KSV12[7:0] 0xBD[7:0]: KSV12[15:8] 0xBE[7:0]: KSV12[23:16] 0xBF[7:0]: KSV12[31:24] 0xC0[7:0]: KSV12[39:32] KSV13[39:0] 0xC1[7:0]: KSV13[7:0]...

  • Page 180: Table 31: Registers Location For Sha-1 Hash Value V

    ADV7604 Register Name Register Addresses Number 0xE3[7:0]: KSV19[39:32] KSV20[39:0] 0xE4[7:0]: KSV20[7:0] 0xE5[7:0]: KSV20[15:8] 0xE6[7:0]: KSV20[23:16] 0xE7[7:0]: KSV20[31:24] 0xE8[7:0]: KSV20[39:32] KSV21[39:0] 0xE9[7:0]: KSV21[7:0] 0xEA[7:0]: KSV21[15:8] 0xEB[7:0]: KSV21[23:16] 0xEC[7:0]: KSV21[31:24] 0xED[7:0]: KSV21[39:32] KSV22[39:0] 0xEE[7:0]: KSV22[7:0] 0xEF[7:0]: KSV22[15:8] 0xF0[7:0]: KSV22[23:16] 0xF1[7:0]: KSV22[31:24] 0xF2[7:0]: KSV22[39:32] KSV23[39:0] 0xF3[7:0]: KSV23[7:0] 0xF4[7:0]: KSV23[15:8]...

  • Page 181: Interface To Dpp Section

    ADV7604 7.21 Interface to DPP Section The video data from the HDMI section is sent to the CP section via the DPP block. The video data output by the HDMI section is always in a 4:4:4 format with 36 bits per pixel, irrespective of the encoding format the video data encapsulated in HDMI/DVI stream input to the HDMI section receives (i.e.
  • Page 182 ADV7604 UP_CONVERSION_MODE, HDMI Map, Address 0x1D, [5] This control selects the linear or interpolated 4:2:2 to 4:4:4 conversion performed in the HDMI section. Function UP_CONVERSION Description _MODE Repeats Cr/Cb values. 4:2:2 incoming stream is upconverted to 4:4:4 stream before being sent to DPP section. Cr and Cb samples are repeated in their respective channel.

  • Page 183: Color Space Information Sent To The Dpp And Cp Sections

    ADV7604 / Cb / Cr / Cb / Cr / Cb Component Channel Bit 12-0 Cb/Cr Bit 12-0 Figure 50: Video Data Output by DPP in 4:2:2 Pass Through Mode 7.22 Color Space Information Sent to the DPP and CP Sections The HDMI section sends information regarding the color space of the video it outputs to the DPP and the CP sections.

  • Page 184: Status Registers

    ADV7604 7.23 Status Registers Many status bit are available throughout the IO and HDMI Maps. These status bits are listed in Table Table 32: HDMI Flags in IO Map Register 0x60 Bit Name Bit Position Description AVI_INFO_RAW 1 (LSB) Returns 1 if an AVI InfoFrame was received within last seven VSync.

  • Page 185: Table 34: Hdmi Flags In Io Map Register 0X6A

    ADV7604 Bit Name Bit Position Description with the same type set. Reset to 0 following a packet detection flag reset condition. AUDIO_CH_MD_RAW Returns 1 if the audio channel mode is two channel audio. Reset to 0 following a packet detection flag reset condition.

  • Page 186: Table 37: Hdmi Flags In Io Map Register 0X79

    ADV7604 Bit Name Bit Position Description NEW_AVI_INFO_RAW 0 (LSB) Returns 1 if an AVI InfoFrame with new content has been received. Reset to 0 by setting NEW_AVI_INFO_CLR (IO Map, Address 0x76[0]) to 0. NEW_AUDIO_INFO_RAW Returns 1 if an Audio InfoFrame with new content has been received.

  • Page 187: Table 38: Hdmi Flags In Io Map Register 0X7E

    ADV7604 Bit Name Bit Position Description Map, Address 0x7B[2]) CHANGE_N_RAW Description available here. CTS_PASS_THRSH_RAW Description available here. FIFO_OVERFLO_RAW Description available here. FIFO_UNDERFLO_RAW Description available here. FIFO_NEAR_OVFL_RAW 7 (MSB) Description available here. Table 38: HDMI Flags in IO Map Register 0x7E Bit Name Bit Position Description...

  • Page 188: Hdmi Section Reset Strategy

    ADV7604 Bit Name HDMI Map Description Location SPD_INF_CKS_ERR_ST 0x19[6] Description available here. MS_INF_CKSUM_ERR 0x19[7] Description available here. DCFIFO_LOCKED 0x1C[3] Description available here. 7.24 HDMI Section Reset Strategy The reset strategy implemented for the HDMI section is as follows: • Global Chip Reset A global chip reset is triggered by asserting the RESETB pin to a low level.

  • Page 189: Decimation And Color Space Conversion

    ADV7604 8 Decimation and Color Space Conversion Data Preprocessor The DPP is positioned after the AFE and HDMI receiver. It receives data directly from either the ADCs or from the HDMI receiver section. The DPP block is generally automatically configured by PRIM_MODE[3:0] VID_STD[5:0] controls.

  • Page 190: Decimation Filters

    ADV7604 • This mode is also available for external clock and clamp mode (refer to Section 10.16) when the user needs to reduce delay with no decimation, downsampling, or color space conversion in the DPP block. • The DPP is never bypassed in decimated modes 2x1, 4x2, and 4x1. •...

  • Page 191: Dpp Automatic Selection

    ADV7604 8.3.1 DPP Automatic Selection The ADV7604 has an automatic selection algorithm for the decimation filters in the DPP block. Based on the PRIM_MODE[3:0], VID_STD[5:0], OP_FORMAT_SEL selected, the ADV7604 decides on the best filter mode to be used, as indicated in Table Table 41: DPP Filter Auto Selection Mode of...

  • Page 192: Figure 52: Manual And Default Dcm Filter Response Selection

    ADV7604 DCM_FILT_SEL, DPP Map, Address 0x29, [1:0] DCM_FILT_SEL bit controls the manual selection of the filter response for the decimation filters. For the selection to be effective, manual control must be enabled by DCM_FILT_MAN_EN. Function DCM_FILT_SEL Description Bypass decimation filters DCM filter response with Fc = 0.26 * Fs/2 (blue in Figure DCM filter response with Fc = 0.43 * Fs/2 (red in...

  • Page 193: Decimation Filter Selection For Stage 2

    ADV7604 8.3.3 Decimation Filter Selection for Stage 2 The decimation filters of the A, B, and C channels are 19-tap fully programmable filters. The response for these filters can be automatically or manually selected from a choice of seven predefined filter responses. DPP_FILT_MAN_EN, DPP Map, Address 0x28, [0] DPP_FILT_MAN_EN bit allows the user to switch between the default luma and chroma filter...

  • Page 194: Figure 53: Dpp Predetermined Filter Responses Available In Manual Selection Mode

    ADV7604 Figure 53: DPP Predetermined Filter Responses Available in Manual Selection Mode DPP_CHROMA_LOW_EN, IO Map, Address 0xE7, [4] The DPP_CHROMA_LOW_EN bit allows the user to switch between a high bandwidth signal with a sharp transition curve and a softer filter with less ringing. Function DPP_CHROMA_LOW_EN Description...

  • Page 195: Table 42: Coefficients Of 19-Tap Decimation Filter On Channel A

    ADV7604 8.3.3.1 Manual Configuration of 19-Tap Decimation Filter The z-transform of the 19-tap decimation filter of the second stage of DPP is shown in Equation ∑ − Equation 6: z-Transform of 19-Tap Decimation Filter where: coeff coeff coeff coeff coeff coeff coeff coeff...

  • Page 196: Table 43: Coefficients Of 19-Tap Decimation Filters On Channels B And C

    ADV7604 Coefficients Register Name DPP Map Example of Values for Filter Register Response with Fc = 0.2 * Fs/2 Location of the Hexadecimal Decimal Representation Representation PROG_COEFF4_CHA[11:8] Address 0x06[3:0] Coeff4 0xFDD PROG_COEFF4_CHA[7:0] Address 0x07[7:0] PROG_COEFF5_CHA[11:8] Address 0x08[3:0] Coeff5 0xFDB PROG_COEFF5_CHA[7:0] Address 0x09[7:0] PROG_COEFF6_CHA[11:8]...

  • Page 197: Chroma 4X Decimation Filter Selection In Stage 2

    ADV7604 Coefficient Register Name DPP Map Register Location Coeff7 PROG_COEFF7_CHBC[11:8] Address 0x20[3:0] PROG_COEFF7_CHBC[7:0] Address 0x21[7:0] Coeff8 PROG_COEFF8_CHBC[11:8] Address 0x22[3:0] PROG_COEFF8_CHBC[7:0] Address 0x23[7:0] Coeff9 PROG_COEFF9_CHBC[11:8] Address 0x24[3:0] PROG_COEFF9_CHBC[7:0] Address 0x25[7:0] Coeff10 PROG_COEFF10_CHBC[11:8] Address 0x26[3:0] PROG_COEFF10_CHBC[7:0] Address 0x27[7:0] 8.3.4 Chroma 4x Decimation Filter Selection in Stage 2 CHROMA4X_MAN_EN, DPP Map, Address 0x28, [4] CHROMA4X_MAN_EN bit allows the user to switch between the default chroma decimation...

  • Page 198: Dpp Decimation Only Selection

    ADV7604 Figure 54: Chroma 4x Filter Responses in Manual Selection Mode 8.3.5 DPP Decimation Only Selection DS_WITHOUT_FILTER, IO Map, Address 0xE0, [7] In some systems, it may be desirable to downsample on channels B and C without any filter operation. To achieve this, the DS_WITHOUT_FILTER bit can be selected.

  • Page 199: Figure 55: Channel B/C Decimation By 2 For Fs = 13.5 Mhz

    ADV7604 Figure 55: Channel B/C Decimation by 2 for Fs = 13.5 MHz Note: The channel B/C decimation filters (refer to Figure 55) emphasize the stop band to facilitate RGB (4:4:4) to YPbPr (4:2:2) conversion. Figure 56: Default Channel B/C Decimation by 2 with DPP_CHROMA_LOW_EN = 1 for Fs = 13.5 MHz Rev.

  • Page 200: Figure 57: Default Channel A/D Decimation By 2, Channel B/C Decimation By 2 And 4 For Fs = 27 Mhz

    ADV7604 Figure 57: Default Channel A/D Decimation by 2, Channel B/C Decimation by 2 and 4 for Fs = 27 MHz Figure 58: Default Channel A/D Decimation by 2, Channel B/C Decimation by 2 and 4 with DPP_CHROMA_LOW_EN = 1 for Fs = 27 MHz Rev.

  • Page 201: Figure 59: Default Channel A/D Decimation By 4, Channel B/C Decimation By 4 And 8 For Fs = 54 Mhz

    ADV7604 Figure 59: Default Channel A/D Decimation by 4, Channel B/C Decimation by 4 and 8 for Fs = 54 Figure 60: Default Channel A/D Decimation by 4, Channel B/C Decimation by 4 and 8 with DPP_CHROMA_LOW_EN = 1 for Fs = 54 MHz Rev.

  • Page 202: Color Space Conversion Matrix

    ADV7604 Color Space Conversion Matrix The ADV7604 features two 3x3 Color Space Converters (CSC); one in the DPP block (DPP CSC) and the other in the CP block (CP CSC), as shown in Figure 61. The two CSCs provide any-to-any color space support, that is, they support formats such as RGB, YUV, YCrCb, and many other color spaces.

  • Page 203: Cp Csc Or Dpp Csc Selection

    ADV7604 8.4.1 CP CSC or DPP CSC Selection Selection of the CSC conversion in DPP or the CP CSC block is controlled by the following bits: • CP_CSC_MAN_EN • CP_CSC_EN • SWAP_CSC_COEFF The CP CSC is controlled by the CP_CSC_EN_MAN CP_CSC_EN bits.

  • Page 204: Selecting Auto Or Manual Csc Conversion Mode

    ADV7604 SWAP_CSC_COEFF, CP Map, Address 0x69, [3] SWAP_CSC_COEFF selects whether or not the DPP CSC block will do a color space conversion. When SWAP_CSC_COEFF is set, the DPP CSC implements a color space conversion, as defined by the automatic or manual CSC settings (refer to Section 8.4.1). The default values of these coefficients implement a bypass mode and allow a pass through of the data.

  • Page 205: Auto Color Space Conversion Matrix

    ADV7604 8.4.3 Auto Color Space Conversion Matrix The CSC matrix, AGC target gain values, and offset values can be automatically configured via the following set of registers: • INP_COLOR_SPACE[3:0] • RGB_OUT • ALT_GAMMA • OP_656_RANGE_SEL INP_COLOR_SPACE[3:0], IO Map, Address 0x02, [7:4] INP_COLOR_SPACE[3:0] sets the input color space to the CSC when it operates in automatic mode.

  • Page 206: Table 45: Automatic Csc Selection

    ADV7604 RGB_OUT, IO Map, Address 0x02, [1] RGB_OUT is used in conjunction with the INP_COLOR_SPACE[3:0] and ALT_GAMMA bits to select the applied CSC (refer to Table 45). It sets up the output color space and the correct digital blank level and offsets on the RGB or YPrPb outputs. Function RGB_OUT Description...

  • Page 207: Table 46: Csc Configuration For All Csc Modes Reported By Csc_Coeff_Sel_Rb

    ADV7604 CSC_COEFF_SEL_RB[3:0], CP Map, Address 0xFC, [7:4], Read only CSC_COEFF_SEL_RB[3:0] allows the read back of the front-end CSC mode. Refer to Table Function CSC_COEFF_SEL Description _RB[3:0] 0000 CSC set in bypass mode 0001 YPbPr 601 to RGB 0011 YPbPr 709 to RGB 0101 RGB to YPbPr 601 0111...

  • Page 208: Hdmi Auto Csc Operation

    ADV7604 8.4.4 HDMI Auto CSC Operation In HDMI mode, the ADV7604 provides an automatic CSC function based on the AVI InfoFrame sent from the source. The flowchart in Figure 63 shows the mechanism of ADV7604 auto CSC functionality in HDMI mode. START START Detect YCbCr/RGB...

  • Page 209: Figure 65: Adv7604 Hdmi Auto Csc Flowchart (Case Ycbcr-1)

    ADV7604 Y[1:0] = 01b, 10b, 11b Y[1:0] = 01b, 10b, 11b YCbCr Mode YCbCr Mode YCbCr Colorimetry YCbCr Colorimetry C[1:0] = xxb? C[1:0] = xxb? C[1:0] = 10b C[1:0] = 10b C[1:0] = 01b C[1:0] = 01b C[1:0] = 00b C[1:0] = 00b C[1:0] = 11b C[1:0] = 11b...

  • Page 210: Figure 67: Adv7604 Manual Rgb Range Control Flowchart For Auto Csc (Case Rgb)

    ADV7604 Y[1:0] = 00b Y[1:0] = 00b RGB 4:4:4 Mode RGB 4:4:4 Mode Detect Quantization Range Detect Quantization Range Q[1:0] = xxb? Q[1:0] = xxb? Q[1:0] = 00b Q[1:0] = 00b Q[1:0] = 01b Q[1:0] = 01b Q[1:0] = 10b Q[1:0] = 10b 1bit Control QZERO_ITC_DIS= 0...

  • Page 211: Manual Color Space Conversion Matrix

    ADV7604 QZERO_RGB_FULL, HDMI Map, Address 0x47, [1] This bit is used to decode the HDMI colorimetry based when the AVI InfoFrame field Q[1:0] = 2b00. This is valid only when QZERO_ITC_DIS is set. Function QZERO_RGB_FU Description RGB range is set to limited in the case of Q[1:0] = 2b00 RGB range is set to full in the case of Q[1:0] = 2b00 Note: The QZERO_ITC_DIS...

  • Page 212: Table 47: Csc Coefficients

    ADV7604 Table 47: CSC Coefficients Function CP Map Address Reset Value (Hex) Description A1[12:0] 0x57 [4:0], 0x58 [7:0] 0x800 Coefficients for channel A A2[12:0] 0x55 [1:0], 0x56 [7:0] 0x000 A3[12:0] 0x54 [6:0], 0x55 [7:2] 0x000 B1[12:0] 0x5E [4:0], 0x5F [7:0] 0x000 Coefficients for channel B B2[12:0]...
  • Page 213 ADV7604 8.4.5.1 CSC Manual Programming The equations performed by CSC for both DPP and CP CSC are as follows: ⎡ ⎤ ∗ ∗ ∗ ∗ scale ⎢ ⎣ ⎥ ⎦ 4096 4096 4096 Equation 7: CSC Channel A ⎡ ⎤ ∗...
  • Page 214 ADV7604 4. Program the offset values. Depending on the type of CSC, offsets may have to be used. Program A4, B4, C4. 8.4.5.2 CSC Example The following set of equations gives an example of a conversion from a gamma corrected RGB signal into a YCrCb color space signal.
  • Page 215 ADV7604 − − ∗ ∗ ∗ − ∗ ∗ − ∗ 2048 2048 Note: The scaling of the dynamic range does not affect the static offset. Check the value of each coefficient: The maximum value for each coefficient on its own can only be within the range of -4095/4096 to 4095/4096, which equals [-0.999755859375 ..

  • Page 216: Csc In Pass-Through Mode

    ADV7604 8.4.6 CSC in Pass-through Mode It is possible to configure the CSC that is used (i.e. the CP CSC or the DPP CSC) in a pass-through mode. In this mode, the CSC selected via CP_CSC_EN is used but does not alter the data it processes.

  • Page 217: Color Controls

    ADV7604 Color Controls The ADV7604 has a color control feature that can adjust the brightness, contrast, saturation, and hue properties. This feature can only be applied when the CP CSC block is implementing one of the following color space conversions: •...
  • Page 218 ADV7604 0x00 Gain on chroma channel = 0 0xFF Gain on chroma channel = 1.99 CP_BRIGHTNESS[7:0], CP Map, Address 0x3C, [7:0] This function provides a user control for the brightness adjustment. It is a signed number and a gain of 4 is applied to the programmed value to provide a range of -512 to 508. Function CP_BRIGHTNESS[7:0] Description...

  • Page 219: Enhanced Standard Definition Processor

    ADV7604 Enhanced Standard Definition Processor Background The Enhanced Standard Definition Processor (ESDP) is designed to provide robust synchronization separation capability for component video input modes that are likely to have an unstable time base. These signals are component signals that have originated from CVBS signals, such as noisy/weak RF signals or VCR signals with head-switches.

  • Page 220: Clamp And Gain

    ADV7604 Input Input Line Locked Data Line Locked Data Video Video Pb/B Pb/B Pb/B Pb/B Clamp Clamp Pb/B Pb/B Pr/R Pr/R Pr/R Pr/R (x3) (x3) (x3) (x3) Pr/R Pr/R CP Core CP Core I²C I²C Sync Slicing Sync Slicing Control Control Sliced Sync Sliced Sync...

  • Page 221: Input Signal Detection

    ADV7604 Input Signal Detection The ESDP contains circuitry for identifying characteristics of the input signal. The status readback from this circuitry are used within the device to automatically configure it optimally for each input. The detections done include: • Presence/absence of a video-like signal on the input (series of synchronization type shapes at regular intervals).

  • Page 222: Output Timing Signals

    ADV7604 after the ADV7604 adjusts the picture down by four lines to compensate for this four line delay on output timing. This is typically quite easy for a backend chip to do and results in a stable picture with correct vertical position. Output Timing Signals Although there are many registers to control ESDP output timing signals, limited programming is required for most applications supporting standard timing requirements.

  • Page 223: Basic Control - Enabling/Disabling Esdp Mode

    ADV7604 Control ESDP Map Address Adjusts VS_V_END_E_ADJ[5:0] 0xAB[5:0] VSync end position for even field DE_V_BEG_O_ADJ[5:0] 0xAC[5:0] DE start position for odd field DE_V_BEG_E_ADJ[5 :0] 0xAD[5:0] DE start position for even field DE_V_END_O_ADJ[5 :0] 0xAE[5:0] DE end position for odd field DE_V_END_E_ADJ[5 :0] 0xAF[5:0] DE end position for even field All the above controls (with the exception of HS_WIDTH) are signed twos complement adjustments...

  • Page 224: Nonstandard Samples Per Line

    ADV7604 Important: • For a nonstandard PLL_DIV_RATIO[12:0] setting, for example, 910 instead of 858, additional ESDP registers need to be programmed, as outlined in Section 9.10. • The CP CSC is automatically enabled in ESDP mode (refer to Section 8.4.1) and configured in automatic mode, as defined in Section 8.4.2.

  • Page 225: Esdp Free Run Mode

    ADV7604 Table 49: ESDP Setup Examples Function 480i 1x1 480i 2x1 480i 4x1 480i 1x1 480i 1x1 (WXGA) (1080) ADC sampling clock 13.5 MHz 27 MHz 54 MHz 25.6 MHz 36 MHz ADC samples per line 1716 3432 1628 2288 O/P samples per line 1628 2288...

  • Page 226: Component Processor

    ADV7604 10 Component Processor Component Processor Sync Source and Sync Processing Standard Polarity Identification Channel 1 Detection (STDI) (SSPD) HS/VS/F Sync Extractor output Sync Source and Sync Processing Polarity Standard Channel 2 Detection Identification (SSPD) (STDI) video data CHA, CHB & MV &...

  • Page 227: Clamp Operation

    ADV7604 The CP also has the following capabilities: • Generates HSync, VSync, FIELD, and Data Enable (DE) timing reference outputs • Detects the source from which the video is to be synchronized • Measures noise and calibration levels • Measures the depth of the horizontal synchronization pulse used for AGC •...
  • Page 228 ADV7604 The CP contains a digital fine clamp block. Its main purposes are: To compensate for variations of the voltage clamps in the analog domain To allow a clamp to operate even if the input signal is coming from a digital source, for example, external ADC, HDMI/DVI receiver, and so on The digital fine clamp operates in three separate feedback loops, one for each channel.
  • Page 229 ADV7604 CLMP_A[11:0] Manual Clamp Value for Channel A , CP Map, Address 0x6C, [3:0]; Address 0x6D, [7:0] Note : To change the CLMP_A[11:0] value, registers 0x6C and 0x6D must be written to in this order with no other I C access in between. Function CLMP_A[11:0] Description...

  • Page 230: Cp Gain Operation

    ADV7604 CLAMP_AVG_FCTR[1:0] Manual Clamp Filtering Modes , CP Map, Address 0xC5, [7:6] The ADV7604 provides a special filter option for the auto clamp mode. The purpose of this filter is to provide a smoothening mechanism when the clamping value for each channel is being changed continuously in significant amounts by the autoclamping mechanism.

  • Page 231: Manual Gain And Automatic Gain Control Selection

    ADV7604 10.3.3 Manual Gain and Automatic Gain Control Selection Figure 72 shows how the gain is applied to the to the video data processes by the CP section. The following gain configurations are available: Automatic Gain configuration in HDMI Mode This configuration is enabled by setting AGC_MODE_MAN to 0 and by setting the part in...

  • Page 232: Figure 72: Cp Automatic Gain Controls

    ADV7604 0-255 if HDMI_COLORSPACE = 0b001 16-235 if HDMI_COLORSPACE = 0b010 16-235 if HDMI_COLORSPACE = 0b011 0-255 if HDMI_COLORSPACE = 0b100 0-255 if HDMI_COLORSPACE = 0b101 0-255 if HDMI_COLORSPACE = 0b110 0-255 if HDMI_COLORSPACE = 0b111 0b1000 to 0b1110 Reserved AGC_MODE_MAN GAIN_MAN HDMI_MODE...

  • Page 233: Manual Gain Control

    ADV7604 10.3.4 Manual Gain Control The automatic gain control (AGC) can be completely disabled by setting the gain control block into a manual mode. By setting the GAIN_MAN bit, the gain factors for channels A, B, and C are no longer taken from the AGC, but are replaced by three dedicated I C registers.
  • Page 234 ADV7604 B_GAIN[9:0] Manual Gain Value for Channel B , CP Map, Address 0x74, [3:0]; Address 0x75, [7:0] Note : To change the B_GAIN[9:0] value, registers 0x74 and 0x75 must be written to in this order with no other I C access in between. Function B_GAIN[9:0] Description...

  • Page 235: Manual Gain Filter Mode

    ADV7604 10.3.5 Manual Gain Filter Mode The ADV7604 provides a special filter option for the manual gain mode. This is functional only when manual gain is enabled. The purpose of this filter is a smoothing mechanism when the manual gain value is updated continuously by an external system based on either external or readback conditions in the ADV7604.
  • Page 236 ADV7604 the full digitized waveform (including synchronizations) within the 12-bit output range. For this application, the AGC_TAR[9:0] value is very important. For more information, refer to Section 10.4. SyncHeight − • Code Code White Black VideoHeigh Equation 11: CP AGC Target Value Note: The 12-bit target code for white is nominally 940, the target code for black is 64.
  • Page 237 ADV7604 AGC_FREEZE AGC Freeze Enable , CP Map, Address 0x71, [4] Function AGC_FREEZE Description AGC loop operational AGC loop frozen (no further updates, last gain value becomes static) AGC_TIM[2:0] AGC Time Constant Selection , CP Map, Address 0x71, [2:0] Function AGC_TIM[2:0] Description 100 lines...
  • Page 238 ADV7604 CP_AGC_GAIN[9:0] AGC Gain Read Back , CP Map, Address 0xE0, [1:0]; Address 0xE1, [7:0] Function CP_AGC_GAIN[9:0] Description xx xxxx xxxx Readback value of actually used gain on the data of channel A. Data format is 1.9 binary format and composed of one integer and nine fractional bits.

  • Page 239: Cp Peak Active Video Readback

    ADV7604 OP_656_RANGE , IO Map, Address 0x02, [2] This bit decides the output range of the digital data. The OP_656_RANGE setting automatically sets the gain setting, offset setting, and the data saturator setting. The settings applied depend on the type of video signal and whether the signal is routed from the analog front end or from the HDMI receiver.
  • Page 240 ADV7604 The ADV7604 itself does not provide a peak-white AGC. It merely monitors the clamped and gained input signal for the largest video code encountered in each of the three channels and presents this video code for readback via the I C.

  • Page 241: Cp Offset Block

    ADV7604 10.4 CP Offset Block The offset block consists of three independent adders, one for each channel. Using the OFFSET, B_OFFSET, and C_OFFSET registers, a fixed offset value can be added to the data. The actual offset used can come from two different sources: The ADV7604 includes an automatic selection of the offset value, dependent on the CSC mode that is programmed by the user.

  • Page 242: Av Code Block

    ADV7604 • ADV7604 employs sequencers for the offset values that prohibit intermediate wrong values to be applied. • The I C sequencer treats the three offset values as separate entities. To update all three offset values, a single sweep of I C writes to the CP Map, registers 0x77, 0x78, 0x79, and 0x7A is sufficient.
  • Page 243 ADV7604 • The AV codes can be output on all channels or spread across the Y and PrPb buses for 20- bit output modes. • The F and V bits within the codes can be inserted directly or can be inverted before insertion.

  • Page 244: Figure 74 Av Code Output Options (Cp)

    ADV7604 GR_AV_BL_EN, Auto-graphics AV Blanking Control , CP Map, Address 0x81, [4] Function GR_AV_BL_EN Description Data blanking and AV code insertion for auto graphics mode disabled Data blanking and AV code for auto graphics mode enabled DE_WITH_AVCODE, AV Code Insertion Control , CP Map, Address 0x7B, [0] Function DE_WITH_AVCODE Description...

  • Page 245: Cp Data Path For Analog And Hdmi Modes

    ADV7604 10.6 CP Data Path for Analog and HDMI Modes Figure 75 Figure 79 depict the data path of the video for both analog and HDMI modes. These figures depict the gains and offsets applied when using the automatic control, OP_656_RANGE, and the manual options for setting the clamp level, gain, and offset.

  • Page 246: Figure 75: Cp Data Path Channel A (Y) For Analog Mode

    ADV7604 Analog Input measured value CLAMP MEASUREMENT 12-bit unsigned CLAMP CLMP_A[11:0] 12-bit 12-bit 12-bit CLMP_A_MAN AGC_MODE_MAN 13-bit signed GAIN_MAN A_GAIN[9:0] PREGAIN GAIN agc-gain 10-bit 10-bit 10-bit auto-value 10’d502 (x1.96) 10’d586 (x2.29) 15-bit signed SSPD detected embedded syncs A_OFFSET[9:0] 10’d64 OFFSET 10’d0 10-bit 10-bit...

  • Page 247: Figure 76: Cp Data Path Channel B/C (Uv) For Analog Mode

    ADV7604 Analog Input measured-value CLAMP MEASUREMENT 12-bit unsigned CLAMP CLMP_B[11:0]/CLMP_C[11:0] 12-bit CLMP_BC_MAN AGC_MODE_MAN 13-bit signed GAIN_MAN A_GAIN[9:0] PREGAIN GAIN agc-gain 10-bit 10-bit 10-bit auto-value 10’d502 (x1.96) 10’d586 (x2.29) SSPD detected 15-bit signed embedded syncs B_OFFSET[9:0]/C_OFFSET[9:0] 10’d64 OFFSET 10’d0 10-bit auto-value 10’d512 10’d512 235@8-bit...

  • Page 248: Figure 77: Cp Data Path Channel A/B/C (Rgb) For Analog Mode

    ADV7604 Analog Input measured-value CLAMP MEASUREMENT 12-bit unsigned 12-bit unsigned CLAMP CLMP_A[11:0]/CLMP_B[11:0]/CLMP_C[11:0] 12-bit 12-bit 12-bit CLMP_A_MAN/CLMP_BC_MAN AGC_MODE_MAN 13-bit signed 13-bit signed GAIN_MAN A_GAIN[9:0] PREGAIN GAIN agc-gain 10-bit 10-bit 10-bit auto-value 10’d502 (x1.96) 10’d586 (x2.29) SSPD detected 15-bit signed embedded syncs A_OFFSET[9:0]/B_OFFSET[9:0]/C_OFFSET[9:0] 10’d64/10’d64/10’d64 OFFSET...

  • Page 249: Figure 78: Cp Data Path Channel A (Y) For Hdmi Mode

    ADV7604 HDMI Input HDMI measured-value CLAMP MEASUREMENT 12-bit unsigned CLAMP CLMP_A[11:0] 12-bit 12-bit RGB_OUT CLMP_A_MAN 12’d0 HDMI_CLMP_ENABLE auto-value 12’d2056 (16@8-bit) AGC_MODE_MAN 13-bit signed 13-bit signed GAIN_MAN A_GAIN[9:0] PREGAIN OP_656_SEL GAIN 10’d220 (x0.86) 10-bit 10-bit 10-bit [0-255]-IN [16-235]-OUT auto-value 10’d256 (x1.00) [0-255]-IN [0-255]-OUT [16-235]-IN [16-235]-OUT 10’d298 (x1.16)

  • Page 250: Figure 79: Cp Data Path Channel B/C For Hdmi Mode

    ADV7604 HDMI Input HDMI measured-value CLAMP MEASUREMENT 12-bit unsigned CLAMP CLMP_B[11:0]/CLMP_C[11:0] 12-bit 12-bit RGB_OUT CLMP_BC_MAN 12’d0 HDMI_CLMP_ENABLE auto-value 12’d2048 (128@8-bit) AGC_MODE_MAN 13-bit signed 13-bit signed GAIN_MAN B_GAIN[9:0]/C_GAIN[9:0] PREGAIN OP_656_SEL GAIN 10’d220 (x0.86) 10-bit 10-bit 10-bit [0-255]-IN [16-235]-OUT auto-value 10’d256 (x1.00) [0-255]-IN [0-255]-OUT [16-235]-IN [16-235]-OUT 10’d298 (x1.16)

  • Page 251: Synchronization Processed By Cp Section

    ADV7604 10.7 Synchronization Processed by CP Section The following four sources of HSync and VSync are used in the CP core: • ESDP block The sync extracted by the ESDP section are used directly by the CP core when the part runs in ESDP mode.

  • Page 252: Sync Extracted By Sync Slicer Section

    ADV7604 10.7.2 Sync Extracted by Sync Slicer Section The ADV7604 has two sync slicers that can slice one of the two possible embedded sync signals, SYNC1 and SYNC 2. The sliced signals are output on the internal sliced signals EMB_SYNC_SEL_1 EMB_SYNC_SEL_2.

  • Page 253: External Sync And Sync From Hdmi Section

    ADV7604 SYNC_CH2_EMB_SYNC_SEL[1:0] , Channel 2 Embedded Sync Selection, IO Map, Address 0x08, [1:0] Function SYNC_CH2_EMB_ Description SYNC_SEL[1:0] EMB_SYNC_SEL_2 EMB_SYNC_SEL_1 Reserved Reserved 10.7.3 External Sync and Sync from HDMI Section The CP section can receive syncs from the external HSync, VSync and CSync inputs or from the HDMI section, as shown in Figure 82.
  • Page 254 ADV7604 10.7.3.1 Signals Routing to Synchronization Channels The ADV7604 has two synchronization channels. Each channel consists of one SSPD and one STDI section. When an HDMI input is applied, the HDMI core will generate HSync, VSync, and DE signals and supply them as input to the each synchronization channel shown in Figure 82.
  • Page 255 ADV7604 SYNC_CH2_VS_SEL[1:0] , Channel 2 VSync Select, IO Map, Address 0x08, [3:2] Function SYNC_CH2_VS_SEL Description [1:0] VS_IN2 VS_IN1 Reserved VSync from HDMI source 10.7.3.2 XTAL Clock Registering and Glitch Rejection Filter The XTAL CLOCK REGISTERING BLOCK and DIGITAL GLITCH REJECTION FILTER have two outputs for each input.

  • Page 256: Final Sync Muxing Stage

    ADV7604 DIG_SYNC_DEGLITCH_REDUCE_MAN, CP Map, Address 0xF5, [2] Function DIG_SYNC_DEGLITCH_R Description EDUCE_MAN Deglitch filter configured in automatic mode. Deglitch filters before the SSPD sections automatically remove any sync signals less than five XTAL clocks wide for component inputs up to and including 1080i, and sync signals that are less than two XTAL clocks wide for component input 1080p and graphics standards.

  • Page 257: Synchronization Processing Channel Mux

    ADV7604 As described in Section 10.7, there are two main sources for sync information into the CP core, the ESDP block, and one of the SSPD blocks. Figure 82 shows the final stage of muxing, which selects the syncs to be used in the CP core. When ESDP mode is selected and ESDP_MODE set to 0b1, the HS and VS from ESDP are passed...
  • Page 258 ADV7604 The registers that control the synchronization signals routed to each synchronization channel are described in Section 10.7.2 and Section 10.7.3.1. The output from one synchronization channel is used to provide timing to the CP core. The method that is used to determine the sync channel that is used to output sync signals to the CP core is determined by SYNC_CH_AUTO_MODE.

  • Page 259: Synchronization Source Polarity Detector

    ADV7604 SEL_SYNC_CHANNEL , Sync Channel Selected, IO Map, Address 0x12, [7], Read only Function SEL_SYNC_CHANNEL Description Synchronization channel 2 is being processed by CP core Synchronization channel 1 is being processed by CP core 10.8.1 Synchronization Source Polarity Detector Section 10.7 describes how the various synchronization signals are routed to the two synchronization processing channels.

  • Page 260: Figure 84: Sspd Auto Detection Flowchart

    ADV7604 Set CHX_SYN_SRC[1:0] to 00 to enable the autodetection mode Continuous Mode? Set CHX_SSPD_CONT to 0 Set CHX_SSPD_CONT to 1 Set CHX_TRIG_SSPD to 0=>1 the SSPD state machine will run (positive transition on bit) continuously This triggers the SSPD state machine SSPD Block examines input (flags this by setting...
  • Page 261 ADV7604 CH2_TRIG_SSPD Trigger Synchronization Source and Polarity Detector for channel 2 , CP Map, Address 0x41, [2] Function CH2_TRIG_SSPD Description 0 to 1 transition on CH2_TRIG_SSPD causes channel 2 SSPD block to examine currently presented synchronization signals. CH2_TRIG_SSPD bit is not self clearing – must be reset by user to prepare for next trigger. CH1_SYNC_SRC[1:0] SSPD Synchronization Source Selection for channel 1 , CP Map, Address 0x85, [4:3] Function...
  • Page 262 ADV7604 CH1_POL_VS Manual Overwrite for Polarity of VSync SSPD in channel 1 , CP Map, Address 0x85, [6] Function CH1_POL_VS Description VSync input to channel 1 carries negative polarity signal. CH1_POL_MAN_EN must be set high for this bit to become active. VSync input to channel 1 carries positive polarity signal.
  • Page 263 ADV7604 10.8.1.1 SSPD Readback Signals CH1_SSPD_DVALID SSPD Read Back Values Valid Read Back in channel 1 , CP Map, Address 0xB5, [7], Read only CH1_SSPD_DVALID is set to 1 when the read backs from the SSPD section of the synchronization channel 1 are valid.
  • Page 264 ADV7604 CH1_CUR_POL_HS Currently Detected Polarity of HSync SSPD for channel 1 , CP Map, Address 0xB5, [3], Read only Function CH1_CUR_POL_HS Description HSync input to channel 1 SSPD has positive polarity HSync input to channel 1 SSPD has negative polarity CH2_CUR_POL_HS Currently Detected Polarity of HSync SSPD for channel 2 , CP Map, Address 0x4F, [3], Read only Function...
  • Page 265 ADV7604 CH1_CUR_POL_VS Currently Detected Polarity of VSync SSPD for channel 1 , CP Map, Address 0xB5, [5], Read only Function CH1_CUR_POL_VS Description VSync input to channel 1 has positive polarity signal VSync input to channel 1 has negative polarity signal CH2_CUR_POL_VS Currently Detected Polarity of VSync SSPD for channel 2 , CP Map, Address 0x4F, [5], Read only Function...

  • Page 266: Figure 85: Sspd Vsync And Hsync Monitoring Operation

    ADV7604 Field 3 or Line 3 Field 4 or Line 4 Field 5 or Line 5 Field 6 or Line 6 Field 7 or Line 7 crystal clock cycles window SSPPD monitors activity on each sync signal VS and HSover a 2 crystal clock cycles window crystal clock cycles window Figure 85: SSPD VSync and HSync Monitoring Operation...

  • Page 267: Standard Detection And Identification

    ADV7604 SSPD_RSLT_CHNGD_CH2_ST , IO Map, Address 0x5C, [4] Function SSPD_RSLT_CHNGD_CH Description 2_ST No change in synchronization input to SSPD section of synchronization channel 2. Interrupt generated for SSPD_RSLT_CHNGD_CH2_ST after SSPD_RSLT_CHNGD_CH2_RAW changed. Bit is cleared by setting SSPD_RSLT_CHNGD_CH2_CLR (IO Map, Address 0x5D[4]) to 1.
  • Page 268 ADV7604 value of FCL multiplied by 256 gives one field length count in 28.6363 MHz (XTAL) clocks. Note : CHx = CH1 or CH2 in the above register descriptions representing channel 1 and channel 2 related registers. By interpreting these four parameters, it is possible to distinguish between the different types of input signals.
  • Page 269 ADV7604 CH1_STDI_CONT Standard Identification Continuous Mode for channel 1 , CP Map, Address 0x86, [1] Function CH1_STDI_CONT Description Channel 1 STDI block operates in single-shot mode (0 to 1 transition on CH1_TRIG_STDI) Channel 1 STDI block runs continuously CH2_STDI_CONT Standard Identification Continuous Mode for channel 2 , CP Map, Address 0x42, [1] Function CH2_STDI_CONT...

  • Page 270: Detailed Mechanism Of Stdi Block Horizontal/Vertical Lock Mechanism

    ADV7604 CH2_TRIG_STDI Trigger Standard Identification for channel 2 , CP Map, Address 0x42, [2] Function CH2_TRIG_STDI Description 0 to 1 transition triggers the channel 2 STDI measurements. Not self clearing, must be reset by the user. 0 does nothing. Not self clearing, must be reset by the user for next trigger. 1 restarts channel 2 STDI measurements.

  • Page 271: Figure 86: Stdi Horizontal Locking Operation

    ADV7604 line 3-line4≦threshold? line 3-line4≦threshold? line 5-line6≦threshold? line 5-line6≦threshold? line 1-line2≦threshold? line 1-line2≦threshold? line 128 line 128 line 129 line 129 line 3 line 3 line 4 line 4 line 5 line 5 line 6 line 6 line 7 line 7 line 8 line 8 line 1...

  • Page 272: Figure 88: Stdi Vertical Locking Operation

    ADV7604 10.8.3.2 STDI Vertical Locking The STDI block compares adjacent field length differences and VSync lengths in line counts and compares them with a threshold. If four consecutive adjacent field lengths (LCF) and line counts in VSync (LCVS) are within the threshold, the STDI vertically locks to the incoming video. Field2–...
  • Page 273 ADV7604 CH2_BL[13:0], Block Length for channel 2 Read Back , CP Map, Address 0x49, [5:0]; Address 0x4A, [7:0] Function CH2_BL[13:0] Description xx xxxx xxxx xxxx Number of 28.6363 MHz (XTAL frequency) cycles in a block of eight lines of incoming video. Data only valid if CH2_STDI_DVALID high.

  • Page 274: Figure 90: Stdi Usage Flowchart

    ADV7604 CH1_STDI_INTLCD , CP Map, Address 0xB1, [6] Function CH1_STDI_INTLCD Description Indicates a video signal on channel 1 with non interlaced timing. The readback from this register is valid if CH1_STDI_DVALID is high. Indicates a signal on channel 1 with interlaced timing. The readback from this register is valid if CH1_STDI_DVALID is high.

  • Page 275: Table 54: Stdi Readback Values For Sd, Pr, And Hd

    ADV7604 10.8.3.4 STDI Readback Values for SD, PR, and HD Table 54: STDI Readback Values for SD, PR, and HD Standard CHx_BL[13:0] CHx_LCF[10:0] CHx_LCVS[4:0] FCL[12:0] 28.63636 MHz 28.63636 XTAL XTAL 720p SMPTE 296M 5091 4 to 5 1868 1125i SMPTE 274M 6788 562 to 563 4 to 5...

  • Page 276: Figure 91: Stdi Values For Gr Mode (Plot)

    ADV7604 Standard CHx_BL[13:0] CHx_LCF[10:0] CHx_LCVS[4:0] FCL[12:0] 28.63636 MHz 28.63636 XTAL XTAL XGA 60 4726 800 to 806 0 to 6 1868 SVGA 72 4756 660 to 666 0 to 6 1554 SVGA 75 4878 622 to 625 0 to 3 1493 VGA 85 5286...

  • Page 277: Cp Output Synchronization Signal Positioning

    ADV7604 10.9 CP Output Synchronization Signal Positioning The ADV7604 overall synchronization processing flow is shown in the block diagram in Figure The user can reposition the synchronization signal output from the regenerated input synchronization signal within the CP block with the control bits marked in red in Figure sync_ch1_hs_sel[1:0] sync_ch1_vs_sel[1:0]...

  • Page 278: Figure 93: Synchronization Repositioning And Displayed Area

    ADV7604 • DE (indicates active region) shared with the FIELD pin Timing reference signals with shared pins are controlled via I Table 56: CP Synchronization Signal Output Pins Pin Name Primary Signal Secondary Signal Controlled by I C Bit (Default) HS/CS HSync out CSync out...

  • Page 279: Cp Primary Synchronization Signals

    ADV7604 10.9.1 CP Primary Synchronization Signals The three primary synchronization signals have certain default positions, depending on the video standard in use. To allow for a seamless interface to downstream ICs, there is the facility to adjust the position of edges on the three primary synchronization signals.

  • Page 280: Table 58: Hs Default Timing (Continued 1)

    ADV7604 Table 58: HS Default Timing (Continued 1) Symbol Characteristic Note 680x480 640x480 640x480 640x480 at 60 Hz at 72 Hz at 75 Hz at 85 Hz HS to start of active video Default All values are for 1x outputs HS width Default Active video samples...

  • Page 281: Figure 94: Hs Timing

    ADV7604 Rev. F August 2010...
  • Page 282 ADV7604 START_HS[9:0] Start HS Signal , CP Map, Address 0x7C, [3:2] and Address 0x7E, [7:0] This word operates in a twos compliment mode. Shifting the leading edge of the HSync towards active video is achieved by selecting from the range 0x000 to 0x1FF. Shifting the leading edge of the HSync away from active video is achieved by selecting from the range 0x200 to 0x3FF.

  • Page 283: Vsync Timing Controls

    ADV7604 EIA_861_COMPLIANCE , CP Map, Address 0x69, [2] This bit set the start of the VBI for the 525p standard only. Function EIA_861_COMPLIANCE Description The VBI region starts on line 1 The VBI region starts on line 523 (The start of VBI region is compliant with the 861 specification) 10.9.3 VSync Timing Controls Programming of the VS timing signals is listed in this section.

  • Page 284: Timing Controls

    ADV7604 END_VS[3:0] End VS Signal , CP Map, Address 0x7F, [7:4] This 4-bit word operates in a twos compliment mode. Shifting the trailing edge of the VSync towards active video is achieved by selecting from the range 0x0 to 0x7. Shifting the trailing edge of the VSync away from active video is achieved by selecting from the range 0x8 to 0xF.

  • Page 285: Field Timing Controls

    ADV7604 DE_V_START[3:0] , CP Map, Address 0x8E[7:4] This bit is used to adjust the start of the VBI position. Function DE_V_START[3:0] Description 0000 Adjusts start of VBI position DE_V_END[3:0] , CP Map, Address 0x8E[3:0] This bit is used to adjust the end of the VBI position. Function DE_V_END[3:0] Description...
  • Page 286 ADV7604 START_FO[3:0] Start FIELD Odd Signal , CP Map, Address 0x80, [3:0] This 4-bit word operates in a twos compliment mode. Shifting the Start FIELD Odd edge towards active video is achieved by selecting from the range 0x0 to 0x7. Shifting the Start FIELD Odd edge away from active video is achieved by selecting from the range 0x8 to 0xF.

  • Page 287: Figure 95: 525I Vs Timing

    ADV7604 Rev. F August 2010...

  • Page 288: Figure 96: 625I Vs Timing

    ADV7604 Rev. F August 2010...

  • Page 289: Figure 97: 525P Vs Timing

    ADV7604 Rev. F August 2010...

  • Page 290: Figure 99: 720P Vs Timing

    ADV7604 Rev. F August 2010...

  • Page 291: Figure 100: 1080I Vs Timing

    ADV7604 Rev. F August 2010...

  • Page 292: Figure 101: 1080P Vs Timing

    ADV7604 Rev. F August 2010...

  • Page 293: Secondary Synchronization Signals

    ADV7604 10.9.6 Secondary Synchronization Signals The secondary synchronization signals share their output pins with the primary ones, as shown in Table 56. The CSync signal is a logic combination of HSync and VSync. Its polarity can be inverted using the INV_HS_POL bit.

  • Page 294: Figure 102: Ancillary Synchronization Information Output On Vs/Field Pin

    ADV7604 The SSPD decides between embedded synchronization and digital input. Refer to Section 10.8 details on the SSPD. V S _ O U T _ S E L F R E E _ R U N S S P DR e s u l t f r o m S e le c t e d S y n c C h a n n e l V S E xt r a c tio n D S _ O U T S lic e d S y n c f r o m S e le c t e d C h a n n e l...
  • Page 295 ADV7604 1. A raw HSync signal with no polarity detection. This raw HSync signal can be passed straight through to the RAW_SYNC pin by selecting SEL_RAW_CS = 0 and PWR_SAVE_MODE = 0. 2. A circuit that extracts HSync from an applied CSync signal or embedded synchronization signal.

  • Page 296: Cp Horizontal Lock Status

    ADV7604 SEL_RAW_CS Selected D igital H S in put (W itho ut p olarity C o rrection ) PWR_S AVE_MODE C sync or G en H sync em bed ded sync W itho ut M acroVision (Synchrono us to Xtal) Selected D igital H S input ( N e gative P olarity) AN D...

  • Page 297: Figure 104: Synchronization Lock Robustness Measurement

    ADV7604 colour burst video signal HS detection threshold as per ISD_THR[7:0] ISD[8:0] value represents area value Figure 104: Synchronization Lock Robustness Measurement The measurements are taken after the DPP section and before the clamp gain offset on a line-by-line basis on all video lines but not during the VBI. For video lines during the VBI, the result of the last active video line is kept.

  • Page 298: Noise And Calibration

    ADV7604 10.11 Noise and Calibration The ADV7604 provides hardware for a noise and a calibration measurement. The two measurements share some hardware control (window). However, they are different in the way they examine the input data. The measurements are executed during a time window. The window can be positioned anywhere within a line of video and the length can be selected to be 16, 32, 64, or 128 LLC clock cycles.

  • Page 299: Calibration Measurement

    ADV7604 NOISE[7:0] , Noise Measurement Read Back, CP Map, Address 0xE2, [7:0] Function NOISE[7:0] Description xxxxxxxxxxxx Noise measurement result as outlined previously 10.11.3 Calibration Measurement The input signal is accumulated during the measurement window. After the end of the window, the accumulated value is divided by the window length and the result (average signal level over the extent of the window) is presented via the I C register CALIB[10:0].

  • Page 300: Free Run Mode

    ADV7604 10.13 Free Run Mode Free run mode provides the user with a stable clock and predictable data if the input signal cannot be decoded, for example, if input video is not present. It controls default color insertion and causes the ADV7604 to generate a default clock.
  • Page 301 ADV7604 CH1_FR_LL[10:0], CH1 Free-run Line Length , CP Map, Address 0x8F [2:0], Address 0x90 [7:0] CH2_FR_LL[10:0], CH2 Free-run Line Length, CP Map, Address 0x47 [2:0], Address 0x48 [7:0] Free-run Line Length is the horizontal parameter that holds the ideal line length for a given video standard.
  • Page 302 ADV7604 69 lines 134 lines 127 lines 263 lines 255lines CP_LCOUNT_MAX[11:0] Frame Line Count (CP) , CP Map, Address 0xAB, [7:0]; Address 0xAC, [7:4] CH2_FR_FIELD_LENGTH [10:0] Channel 2 Field Line Count (CP) , CP Map, Address 0x46, [7:0]; Address 0x47, [7:5] INTERLACED (CP) , CP Map, Address 0x91, [6] Field Line Count is the vertical parameter that holds the ideal number of lines per field for a given video standard.

  • Page 303: Free Run Feature In Hdmi Mode

    ADV7604 Function CH2_FR_FIELD_L Description ENGTH[10:0 ] 000 00000000 Uses same ideal number of lines reference as channel 1 as dictated by CP_LCOUNT_MAX[11:0] All other values Uses programmed value as ideal number of lines per field in free run decision for channel 2 Function INTERLACED Description...

  • Page 304: Free Run Default Color Output

    ADV7604 HDMI_FRUN_EN , CP Map, Address 0xBA, [0] Function HDMI_FRUN_EN Description Disables free run in HDMI mode Enables free run in HDMI mode HDMI_FRUN_MODE (CP) , CP Map, Address 0xBA, [1] Function HDMI_FRUN_MODE Description HDMI free run mode 0 HDMI free run mode 1 DIS_AUTO_PARAM_BUFF , CP Map, Address 0xC9, [0] The video standard output in HDMI free run mode can be dictated either by the VID_STD[5:0]...
  • Page 305 ADV7604 Mode CP_DEF_COL_MAN_VAL Signal Value CH_A (G) Default – GR CH_B (R) CH_C (B) CH_A (Y) Default – COMP CH_A (Pr) CH_A (Pb) CH_A 4·DEF_COL_CHA[7:0] Man. Override CH_B 4·DEF_COL_CHB[7:0] CH_C 4·DEF_COL_CHC[7:0] CP_ FORCE_FREERUN , CP Map, Address 0xBF, [0] Setting this bit high forces both channel 1 and channel 2 into free run mode. Thus, the CP core is forced into free run and outputs the default color (blue), thus overwriting video data.
  • Page 306 ADV7604 DEF_COL_CHA/B/C[7:0] Manual Default Color Channel A/B/C , CP Map, Address 0xC0, [7:0]; Address 0xC1, [7:0]; Address 0xC2, [7:0] The three parameters DEF_COL_CHA[7:0], DEF_COL_CHB[7:0], and DEF_COL_CHC[7:0] allow the user to specify their own default values. Note: CP_DEF_COL_MAN_VAL must be set high for the three parameters to be used. Refer to Table 63 for more information on the automatic values.

  • Page 307: Cp Status

    ADV7604 10.14 CP Status CP_REG_FFH , CP Map, Address 0xFF, [7:0] This status bit contains status bits for the CP core. Function CP_REG_FF Bit Name Description Reserved Reserved Reserved Reserved CP_FREE_RUN CP is free running (no valid video signal found) Reserved MV_AGC DET Detected Macrovision AGC pulses...

  • Page 308: Auto Graphics Mode

    ADV7604 10.15 Auto Graphics Mode Auto graphics mode is designed to allow the user to configure the ADV7604 to accept an input format not shown in Table 3 with the minimum amount of effort. Auto graphics mode is not limited only to graphics input, it can also be used to support component video input.

  • Page 309: Secondary Auto Graphics Control

    ADV7604 2. AV_POS_SEL, CP Map, Address 0x7B, [2] = 1 AND the following user inputs are set to non zero values. The values set in the user inputs will be used to insert the EAV/SAV time codes and blank the data. 3.
  • Page 310 ADV7604 CP_START_VBI[11:0], CP Map, Address 0xA5, [7:0] and 0xA6, [7:4] CP_START_VBI[11:0] specifies the line number where the VBI region starts. This is used for all fields when the decoder is processing a progressive input, and for odd fields when the decoder is processing an interlaced input.

  • Page 311: Auxiliary Auto Graphics Controls

    ADV7604 CP_END_VBI_EVEN[11:0], CP Map, Address 0xA9 [3:0] and 0xAA, [7:0] CP_END_VBI_EVEN[11:0] specifies the line number where the VBI region ends. This is used for even fields when the decoder is processing an interlaced input and not used when the decoder is processing a progressive input.

  • Page 312: Setting Examples For 1280X720P

    ADV7604 AUTO_SL_FILTER_FREEZE_EN, CP Map, Address 0xCB, [5] This bit determines if the internally generated parameter for the position of the HSync trailing edge is updated during the VBI region. This control is only intended for auto-graphics mode. It is recommended to leave AUTO_SL_FILTER_FREEZE_EN to default. Unless AUTO_SL_FILTER_FREEZE_EN is left to default, the part may generate an incorrect HSync trailing edge position parameter if the input synchronization is embedded and has serration pulses.

  • Page 313: Figure 106: System Delay For External Clock And Clamp Mode

    ADV7604 Figure 106: System Delay for External Clock and Clamp Mode • Regeneration mode The external clamp pulse fed into the ADV7604 is regenerated inside the ADV7604, which enables the user to control the clamp pulse position control of the analog voltage clamp and also the digital fine clamp.

  • Page 314: Clamp Control

    ADV7604 10.16.2 Clamp Control Figure 107 shows the operational block diagram for external clock and clamp mode. DPP_BYPASS_EN clamp ADC0 DPP Block Component Processor Digital Data clamp ADC1 Video Enhancement ADC2 clamp HS/CS Sync VS/FIELD External Clock Control ANVC Conrol Conrol ANVC Control External Clamp...

  • Page 315: Configuring External Clock And Clamp Mode

    ADV7604 10.16.3 Configuring External Clock and Clamp Mode The following register control bits must be configured for external clock and clamp mode operation: • PRIM_MODE[3 :0], IO Map, Address 0x01[3:0] • VID_STD[5:0], IO Map, Address 0x00[5:0] • EXT_CLAMP_DECIM_MODE[1:0], IO Map, Address 0x00[7:6] •...
  • Page 316 ADV7604 The ADV7604 has two main modes of operation: external clamp mode 1 and external clamp mode: • In external clamp mode 1: DFC is enabled for the user to clamp the pedestal level to the lowest digital code by digitally subtracting the digitized synchronization portion.
  • Page 317 ADV7604 EXT_VCLMP_LINE_DLY_EN, CP Map, Address 0xC9, [5] The EXT_VCLMP_LINE_DLY_EN bit enables the user to extend the regenerated clamp positioning in between full 1 line delay versus 1 line – clamp pulse duration. Function EXT_VCLMP_LIN Description E_DLY_EN ANVC/DFC clamp pulse positioning limit to 1 external clock cycle <...

  • Page 318: Figure 108: Regenerated Clamp Pulse Position Control

    ADV7604 Figure 108: Regenerated Clamp Pulse Position Control Rev. F August 2010...
  • Page 319 ADV7604 CP_ANVC_POS_START[12:0], CP Map, Address 0xC6, [7:0], Address 0xCA, [7:4], Address 0xC9, [7] As shown in Figure 107, the start time of the analog voltage clamp relative to the input clamp signal can be controlled by CP_ANVC_POS_START[12:0] with external clock period accuracy in regeneration mode.

  • Page 320: System Delay In Adv7604

    ADV7604 Function CP_DFC_POS_ST Description ART[12:0] x xxxx xxxx xxxx 13-bit position control for DFC start positioning in regeneration mode Notes: • When CP_DFC_POS_START[12:0] is set to 0x0000, the ADV7604 forces ANVC position control with an automatic value of 34 external clock cycles after the selected (set by EXT_VCLMP_POS_EDGE_SEL bit) active clamp pulse edge.

  • Page 321: Table 65: Delay Clock Cycles For Various Operation Modes

    ADV7604 Table 65: Delay Clock Cycles for Various Operation Modes Latency from Latency from DFC Point to Overall Latency Mode of Operation Input to DFC Output Pixel Pins ( A + B ) Point (A) (Bypassed) CP CSC Disabled Ext Clamp Mode (Bypassed) CP CSC...

  • Page 322: Vbi Data Processor

    ADV7604 11 VBI Data Processor The VBI Data Processor (VDP) of the ADV7604 is capable of slicing multiple VBI data standards on component video. The VDP decodes the VBI data on the luma channel of YUV data processed through the CP core. For low data rate VBI standards like CCAP (Closed Captioning), WSS (Wide Screen Signaling), or CGMS (Copy Generation Management System), the user can read the decoded data bytes from dedicated I...

  • Page 323: Vdp Default Configuration

    ADV7604 Table 66: VBI Data Standards VBI_DATA_ 625/50 525/60 525p 625p 720p 1080i STD [3:0] (Interlaced) (Interlaced) Binary Dec 0000 Auto Mode VDP 0001 Teletext system Teletext system Reserved Reserved Reserved Reserved identified by identified by VDP_TTXT_ VDP_TTXT_ TYPE TYPE 0010 VPS –...

  • Page 324: Vdp Manual Configuration

    ADV7604 525i 625i 525p 625p 720p 1080i Line Default Line Default Line Default Line Default Line Default Line Default VBI_ VBI_ VBI_ VBI_ VBI_ VBI_ DATA DATA_ DATA DATA_ DATA_ DATA_ [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] 11.1.2 VDP Manual Configuration The user can configure the VDP to decode different standard(s) on desired line(s) on a line to line basis through manual line programming.
  • Page 325 ADV7604 Register Bit Names Register 525i 625i 1080i 525p, 625p, Location 720p Line Numbers in which VBI Data is Inserted VDP_MAN_LINE_5_25[7:4] 0x68 VDP_MAN_LINE_6_26[7:4] 0x69 VDP_MAN_LINE_7_27[7:4] 0x6A VDP_MAN_LINE_8_28[7:4] 0x6B VDP_MAN_LINE_9_29[7:4] 0x6C VDP_MAN_LINE_10_30[7:4] 0x6D VDP_MAN_LINE_11_31[7:4] 0x6E VDP_MAN_LINE_12_32[7:4] 0x6F VDP_MAN_LINE_13_33[7:4] 0x70 VDP_MAN_LINE_14_34[7:4] 0x71 VDP_MAN_LINE_15_35[7:4] 0x72 21 + Full...

  • Page 326: Full Field/Frame Detection

    ADV7604 11.2 Full Field/Frame Detection Full field/full frame detection (lines other than VBI lines) of any standard can also be enabled by writing into the respective registers for different standards (refer to Table 69). As shown in Table the programmed standard in the following registers will be enabled for all the active lines (full field/frame).

  • Page 327: Vdp Configuration

    ADV7604 VDP_TTXT_TYPE[1:0] (VDP) , VDP Map, Address 0x60, [1:0] VDP_TTXT_TYPE[1:0] specifies the Teletext type to be decoded. These bits are functional only if VDP_TTXT_TYPE_MAN_EN is set to 1. Function VDP_TTXT_TYPE Description [1:0] 625/50 525/60 Teletext-ITU-BT.653- 625/50-A Reserved Teletext-ITU-BT.653- 625/50-B Teletext-ITU-BT.653-525/60- (WST) Teletext-ITU-BT.653- 625/50-C Teletext-ITU-BT.653-525/60-...

  • Page 328: Hamming Code Error

    ADV7604 EN_FC_WINDOW_AFTER_CRI (VDP), VDP Map, Address 0x60, [3] In any line in the VBI region, HSync is followed by color burst, clock run in, CRI, and FC. There are two schemes present to facilitate the correct detection of CRI and FC (color burst and other data must not be detected as CRI/FC).
  • Page 329 ADV7604 Bytes 11 to 42 Raw data bytes Text Packets Byte 1 Mag No. – dehammed byte 4 (X/01 to X/25) Byte 2 Row No. – dehammed byte 5 Bytes 3 to 42 Raw data bytes 8/30 (Format 1) Byte 1 Mag No.
  • Page 330 ADV7604 BIPHASE_DECOD_DISABLE , VDP Map, Address 0x61, [0] There is a biphase decoder in the VDP that is a post processor on the decoded data and is used only for WSS and VPS. If biphase decoder is disabled, the raw elements of the biphase decoded data are given out in the data.

  • Page 331: Adaptive Slice Level Generators

    ADV7604 VDP_CP_CLAMP_AVG , VDP Map, Address 0x61, [7] This bit applies when VBI signals are processed through the CP processor. Function VDP_CP_CLAMP_ Description 16 samples are taken for averaging to calculate clamp levels 32 samples are taken for averaging to calculate clamp levels 11.4.2 Adaptive Slice Level Generators Adaptive slice level generators can use the peak and trough levels for calculating the slice level.

  • Page 332: Vdp Ancillary Data Output

    ADV7604 ADAP2_GEM2X_SWING_EN , VDP Map, Address 0x9B, [5] Function ADAP2_GEM2X_SWING_EN Description Disables adaptive slice level generator for GEM2X standard Enables adaptive slice level generator for GEM2X standard ADAP2_VITC_SWING_EN , VDP Map, Address 0x9B, [6] Function ADAP2_VITC_SWING_EN Description Disables adaptive slice level generator for VITC standard Enables adaptive slice level generator for VITC standard ADAP2_TTXT_SWING_EN , VDP Map, Address 0x9B, [7] Function...

  • Page 333: Nibble Output Mode

    ADV7604 DID6_2 [4:0] (VDP) , VDP Map, Address 0x62 [4:0] Function DID6_2 Description 10101 User specified DID sent in the ancillary stream with VDP decoded data SDID7_2[5:0] (VDP) , VDP Map, Address 0x63, [5:0] Function SDID7_2 Description 101010 User specified SDID sent in the ancillary stream with VDP decoded data TOGGLE_ADF (VDP) , VDP Map, Address 0x63, [7] The VDP can output the ancillary data packets spread across the Y and C buses, or they can be duplicated on both the channels.

  • Page 334: Table 72: Ancillary Data In Nibble Output Format

    ADV7604 calculated value, and B9 as the inverse of B8. The checksum value B8 to B0 is equal to the nine least significant bits of the total sum of the nine least significant bits of the DID, SDID, DC words, and all UDWs in the packet. Prior to the start of the checksum count cycle, all checksum and carry bits are preset to zero.

  • Page 335: Structure Of Vbi Words In Ancillary Data Stream

    ADV7604 Byte Description Ancillary data preamble DID – data identification I2C_DID6_2[4:0] word SDID – secondary data I2C_SDID7_2[5:0] identification word DC[4:0] Data count PADDIN VBI_DATA_STD[3:0] ID0 – user data word 1 G[1:0] LCOUNT[11:6] ID1 – user data word 2 LCOUNT[5:0] ID2 – user data word 3 VDP_TTXT_ ID3 –...

  • Page 336: Framing Code

    ADV7604 11.7.1 Framing Code The length of the actual framing code depends on the VBI data standard. For uniformity, the length of the framing code reported in the ancillary data stream is always 24 bits. For standards with a lesser framing code length, the extra LSB bits are set to 0.

  • Page 337: Data Bytes

    ADV7604 UDW5[5:2] = 4b0010 UDW6[5:2] = 4b0111 UDW7[5:2] = 4b0000 (undefined bits made zeros) UDW8[5:2] = 4b0000 (undefined bits made zeros) UDW9[5:2] = 4b0000 (undefined bits made zeros) UDW10[5:2] = 4b0000 (undefined bits made zeros) For the byte mode: UDW5[9:2] = 8b0010 0111 UDW6[9:2] = 8b0000 0000 (undefined bits made zeros) UDW7[9:2] = 8b0000 0000 (undefined bits made zeros) 11.7.2 Data Bytes...

  • Page 338: Readback Registers

    ADV7604 ADF Mode ID User Framing VBI Data Number of Total Number Standard Data Code Words Padding of User Data Words UDWs Words Words (525i) 01,10 (byte mode) GEMSTAR_2X 00 (nibble mode) (525i) 01,10 (byte mode) CCAP 00 (nibble mode) (525i and 625i) 01,10 (byte mode) 00 (nibble mode)

  • Page 339: Content Based Data Update

    ADV7604 These steps can be summed up in the following pseudo code : // CODE USED BY THE USER FOR SLICED “PDC” DATA READING Byte vdp_status_read_out; vdp_status_addr = 0x78h; vdp_output_sel_addr = 0x9Ch; I2C_write_byte (vdp_output_sel_addr, 0x80h); // CLEARING GS_PDC_VPS_UTC AVL BITS IN VDP_STATUS REG I2C_write_byte (vdp_status_addr, 0x10h);...

  • Page 340: Interrupt Based Reading Of I C Registers

    ADV7604 WSS_CGMS_CB_CHANGE (VDP) , VDP Map, Address 0x9C, [4], WSS_CGMS_CB_CHANGE enables content based update for WSS and CGMS. Function WSS_CGMS_CB_CHANGE Description Disables content based update of WSS, CGMS data Enables content based update of WSS, CGMS data 11.10 Interrupt Based Reading of I C Registers Some VDP status bits are also linked to the interrupt request controller so that the user does not have to poll the available status bit.

  • Page 341: Interrupt Mask Register Details

    ADV7604 11.10.1 Interrupt Mask Register Details CCAP_AVL_MB1 , IO Map, Address 0x54, [0] Function CCAP_AVL_MB1 Description Disables interrupt on INT1 pin for CCAP_AVL signal from VDP Enables interrupt on INT1 pin for CCAP_AVL signal from VDP CCAP_AVL_MB2 , IO Map, Address 0x53, [0] Function CCAP_AVL_MB2 Description...

  • Page 342: Interrupt Status Register Details

    ADV7604 VITC_AVL_MB1 , IO Map, Address 0x54, [6] Function VITC_AVL_MB1 Description Disables interrupt on INT1 pin for VITC_AVL signal from VDP Enables interrupt on INT1 pin for VITC_AVL signal from VDP VITC_AVL_MB2 , IO Map Address 0x53, [6] Function VITC_AVL_MB2 Description Disables interrupt on INT2 pin for VITC_AVL signal from VDP Enables interrupt on INT2 pin for VITC_AVL signal from VDP...

  • Page 343: Interrupt Status Clear Register Details

    ADV7604 11.10.3 Interrupt Status Clear Register Details CCAP_AVL_CLR , IO Map, Address 0x53, [0] Function CCAP_AVL_CLR Description Not necessary to write 0 to this bit as it is a self clearing bit Clears CCAP_AVL_CLR Interrupt Status register bit CGMS_WSS_AVL_CLR , IO Map, Address 0x53, [2] Function CGMS_WSS_AVL_CLR Description...

  • Page 344: Cgms And Wss

    ADV7604 11.11.2 CGMS and WSS The CGMS and WSS convey the same type of information for different video standards. WSS is a 625i standard while CGMS is a 525i, 525p, 625p, 720p, and 1080i standard. Hence, the CGMS and WSS readback registers are shared. WSS is biphase coded and the VDP does a biphase decoding to produce the 14 raw WSS bits to be available in the CGMS and WSS readback I C registers and the CGMS_WSS_AVL bit is set when this data is available.

  • Page 345: Ccap

    ADV7604 Figure 111: CGMS (525i) Waveform 11.11.3 CCAP Two bytes of decoded closed caption data are available in the I C registers. The field information of the decoded CCAP data can be obtained from the CC_EVEN_FIELD bit. STATUS_CLEAR_CCAP , VDP Map, Address 0x78, [0], Write only Function STATUS_CLEAR_CCAP Description...

  • Page 346: Vitc

    ADV7604 VDP_CCAP_DATA_2 VDP Closed Caption Readback 2, VDP Map, Address 0x42, [7:0], Read only Function VDP_CCAP_DATA_2 Description xxxx xxxx Decoded byte 1 of CCAP data[15:8] 0x42[7:0] VDP_CCAP_DATA[15:8] Figure 112: CCAP Waveform and Decoded Data Correlation 11.11.4 VITC VITC has a synchronization sequence of 10 between each data byte. The VDP strips these synchronizations from the data stream to output only the data bytes.

  • Page 347: Vps, Pdc, Utc, Gemstar, And Cgms Type B

    ADV7604 Refreshes the VITC readback registers STATUS_VITC , VDP Map, Address 0x40, [6], Read only Function STATUS_VITC Description VITC not detected VITC detected Table 77: VITC Readback Registers Signal Name Register Location Address (VDP Register Map) Default Value VDP_VITC_DATA_1[7:0] VDP_VITC_DATA[7:0] 0x55 Read only VDP_VITC_DATA_2[7:0]...

  • Page 348: Table 78: Vdp_Gs_Vps_Pdc_Utc_Cgmstb_Data Readback Registers

    ADV7604 Function GS_VPS_PDC_UTC_CG Description MSTB[2:0] CGMS type B 101, 110, 111 Reserved STATUS_CLEAR_GS_VPS_PDC_UTC_CGMSSTB , VDP Map, Address 0x78, [4], SC Function STATUS_CLEAR_GS_VP Description S_PDC_UTC_CGMSSTB Not necessary to write 0 since STATUS_CLEAR_GS_VPS_PDC_UTC_CGMSSTB is a self clearing bit Refreshes the VDP_GS_VPS_PDC_UTC_DATA readback data registers with data type selected with the GS_VPS_PDC_UTC_CGMSTB bits STATUS_GEMS_VPS , VDP Map, Address 0x40, [4], Read only...
  • Page 349 ADV7604 Signal Name Register Location Address Register (VDP Default Map) Value VDP_VPS_PDC_UTC_CGMSTB_DATA VDP_VPS_PDC_UTC_ 0x52 Read _11[7:0] only CGMSTB_DATA _11[7:0] VDP_VPS_PDC_UTC_CGMSTB_DATA VDP_VPS_PDC_UTC_ 0x53 Read _12[7:0] only CGMSTB_DATA _12[7:0] The VPS data bits are biphase decoded by the VDP. The decoded data is available in both the ancillary stream and in the I C register.

  • Page 350: Table 79: Vdp_Cgms_Typeb_Data Readback Registers

    ADV7604 PDC and UTC PDC and UTC is data transmitted through Teletext packet 8/30 format 2 (magazine 8, row 30, desig_code being 2 or 3); and packet 8/30 format 1 (magazine 8, row 30, desig_code being 0 or 1). If PDC/UTC data is to be read through I C, the corresponding Teletext standard should be decoded by VDP.

  • Page 351: Customer Electronic Control

    ADV7604 12 Customer Electronic Control The Customer Electronic Control (CEC) controller features the hardware required to behave as an initiator or a follower as per the specifications for a CEC device. When the CEC controller is used, a host processor (e.g. an external processor controlling the ADV7604) is only required to initialize it, or send or receive CEC messages by accessing the message buffer via the CEC Map.

  • Page 352: Main Controls

    ADV7604 12.1 Main Controls This section describes the main controls for the CEC controller. CEC_POWER_UP, CEC Section Enable , CEC Map, Address 0x2A, [0] Function CEC_POWER_UP Description Disables CEC section Enables CEC section CEC_SOFT_RESET, CEC Reset , CEC Map, Address 0x2C, [0] Function CEC_SOFT_RESE Description...
  • Page 353 ADV7604 Register Name CEC Map Description Address CEC_TX_FRAME_DATA12[7:0] 0x0D Byte 12 of the next outgoing message CEC_TX_FRAME_DATA13[7:0] 0x0E Byte 13 of the next outgoing message CEC_TX_FRAME_DATA14[7:0] 0x0F Byte 14 of the outgoing message CEC_TX_FRAME_LENGTH[4:0], Length of the Next Outgoing Message , CEC Map, Address 0x10, [4:0] Function CEC_TX_FRAME...
  • Page 354 ADV7604 transmit message on CEC bus at same time. CEC transmit has lost arbitration to second initiator. When this bit is set, the transmit section stops transmitting and becomes a follower. CEC_TX_RETRY_TIMEOUT_RAW, CEC Arbitration Lost Raw Status , IO Map, Address 0x4C, [2] Function CEC_TX_RETRY_...

  • Page 355: Figure 115: State Machine Of Cec Transmitter

    ADV7604 Figure 115: State Machine of CEC Transmitter CEC_TX_RETRY[2:0], CEC Transmission Retry Setting , CEC Map, Address 0x12, [6:4] Function CEC_TX_RETRY[ Description 2:0] Number of times transmit module will retransmit a message if transmission fails because follower does not acknowledge message or a low drive is detected on CEC bus Default value CEC_TX_NACK_COUNTER[3:0], CEC Transmission Counter for no Acknowledge , CEC...

  • Page 356: Cec Receiver Module

    ADV7604 12.3 CEC Receiver Module The receiver module is used when the CEC block acts as a follower. The host utilizes the CEC receiver module to receive the broadcast messages or directly addressed messages on the CEC bus. If the host is ready to accept messages, it informs the receive module by setting the CEC_RX_ENABLE register to 1.
  • Page 357 ADV7604 The host must set the destination logical address of the messages that the CEC receive module processes and acknowledges via the following registers: • CEC_LOGICAL_ADDRESS0[3:0] if CEC_LOGICAL_ADDRESS_MASK[0] is set to 1 • CEC_LOGICAL_ADDRESS1[3:0] if CEC_LOGICAL_ADDRESS_MASK[1] is set to 1 •...

  • Page 358: Clock

    ADV7604 IDLE falling edge lowdrive 3.6ms invalid for period error start bit START handle is done valid ERROR start bit RX_DATA is own message || period error bit period timeout EOM bit is done byte is done & frame is not done frame is done || period error bit period timeout...

  • Page 359: Antiglitch Filter Module

    ADV7604 CEC_CLOCK_DIVIDER[7:0], Clock Divider Value , CEC Map, Address 0x2A, [7:0] Function CEC_CLOCK_DIV Description IDER[7:0] xxxxxxxx CEC clock is the Xtal clock divided by value set in this register 00111110 Default value 12.5 Antiglitch Filter Module This module is used to remove the glitches in the CEC bus in order to make the CEC input signal cleaner before it enters the CEC module.

  • Page 360: Using Cec Module As Initiator

    ADV7604 Figure 117: CEC Module Initialization 12.6.2 Using CEC Module as Initiator Figure 118 shows the algorithm that can be implemented in the host processor controlling the ADV7604 in order to use the CEC module as an initiator. Start Write the outgoing CEC command into the outgoing message registers (CEC Map Reg 0x00 to 0x0F) Set CEC_TX_FRAME_LENGTH...

  • Page 361: Using Cec Module As Follower

    ADV7604 12.6.3 Using CEC Module as Follower Figure 119 shows the algorithm that can be implemented in the host processor controlling the ADV7604 in order to use the CEC module as a follower. Figure 119: Using CEC Module as Follower Rev.

  • Page 362: Av.link Bus Interface

    ADV7604 13 AV.link Bus Interface The AV.link controller features the hardware required to acts as an initiator or a follower as per the AV.link specification. When the AV.link controller is used, a host processor (e.g. an external processor controlling the ADV7604) is only required to initialize it, or send or receive AV.link messages by accesses the message buffer via the AV.link Map.

  • Page 363: Main Controls

    ADV7604 13.1 Main Controls This section describes the main controls for the AV.link. AVLINK_POWER_UP, AV.Link Section Enable , AVLINK Map, Address 0x27, [0] Function AVLINK_POWER Description Disables the AV.link section Enables the AV.link section AVL_SOFT_RESET, AV.link Reset , AVLINK Map, Address 0x29, [0] Function AVL_SOFT_RESE Description...

  • Page 364: Figure 121: Av.link Command Block

    ADV7604 AVL_TX_FRAME_MODE[1:0], Outgoing Message Frame Mode , AVLINK Map, Address 0x00, [1:0] Function AVL_TX_FRAME Description _MODE[1:0] Frame mode of next outgoing message (refer to Section 12.5) Default value AVL_TX_FRAME_ECT, Outgoing Message ECT bit , AVLINK Map, Address 0x00, [0] Function AVL_TX_FRAME Description _ECT...
  • Page 365 ADV7604 AVLINK_TX_READY_RAW, AV.link Transmit Module Ready Raw Status , IO Map, Address 0x4C, [4] Function AVLINK_TX_REA Description DY_RAW Last outgoing message failed to be transmitted or/and the AV.link transmit section is not ready yet to transmit a new message Last message in transmitter buffer was transmitted successfully and transmit module is ready to accept and transmit next message AVLINK_TX_ARBITRATION_LOST_RAW, AV.link Arbitration Lost Raw Status , IO Map, Address 0x4C, [5]...

  • Page 366: Av.link Receive Module

    ADV7604 0x50[6]) or AVLINK_TX_ARBITRATION_LOST_MB2 (IO Map, Address 0x4F[6]). Refer to Section for additional information on the interrupt feature. • A corresponding interrupt can be enabled for AVLINK_TX_RETRY_TIMOUT_RAW by setting the mask AVLINK_TX_RETRY_TIMOUT _MB1 (IO Map, Address 0x50[5]) or AVLINK_TX_RETRY_TIMOUT _MB2 (IO Map, Address 0x4F [5]). Refer to Section for additional information on the interrupt feature.

  • Page 367: Table 83: Av.link Incoming Message Buffer Registers

    ADV7604 Table 83: AV.link Incoming Message Buffer Registers Register Name AVLINK Description Address AVL_RX_FRAME_HEADER[7:0] 0x16 Header of the last incoming message AVL_RX_FRAME_DATA0[7:0] 0x17 Byte 0 of the last incoming message AVL_RX_FRAME_DATA1[7:0] 0x18 Byte 1 of the last incoming message AVL_RX_FRAME_DATA2[7:0] 0x19 Byte 2 of the last incoming message AVL_RX_FRAME_DATA3[7:0]...
  • Page 368 ADV7604 AVL_RX_ENABLE, AV.Link Message Transmission Enable , AVLINK Map, Address 0x10, [0] Function AVL_RX_ENABL Description AV.link receive module not ready to receive a message or a message has already been received Host sets this bit to 1 to inform AV.link receive module that it is ready to receive a new message The host must set the destination address of the received message that the AV.link receive module processes and acknowledges via the following registers:...

  • Page 369: Figure 123: Av.link Receiver State Machine

    ADV7604 The ADV7604 features the AVLINK_RX_READY_RAW register, which is set to one when a message is received by the AV.link receive module. AVLINK_RX_READY_RAW, AV.link Receive Module Ready Raw Status , IO Map, Address 0x4C, [7] Function AVLINK_RX_RE Description ADY_RAW Do not use Host set this bit to 1 so that AV.link receive module starts monitoring AV.link for incoming messages.

  • Page 370: Clock

    ADV7604 13.4 Clock Generator Module This module is used to generate the AV.link process clock based on the Xtal clock. The clock divider register is used to control the clock divider factor. The output clock frequency is given by Equation xtal AVLink CLOCK...

  • Page 371: Mode 1

    ADV7604 13.6.1 Mode 1 The format of the mode 1 frame is shown in Figure 124. This mode 1 frame has no ACKs. Start Header Frame_data0 Frame_data1 Figure 124: Mode 1 Frame Format Table 85: Value Taken By Each Data Unit in Mode 1 Frame Frame Type Value (Binary Format)

  • Page 372: Mode Detection

    ADV7604 Table 87: Value Taken by Each Data Unit in Mode 3 Frame Frame Type Value (Binary Format) Header xxxxxbbb Frame data 0 xxbbbbbb Frame data 1 bbbbbbbb Frame data 2 bbbbbbbb Frame data 3 bbbbbbbb Frame data 4 bbbbbbbb Frame data 5 bbbbbbbb Frame data 6...

  • Page 373: Esc/Dir Bit Validation

    ADV7604 mode=INVALID if(bit_counter==0 && sampled_avlink_in==0) mode=1; start_sequence_error=0; else if(bit_counter==1 && sampled_avlink_in==0) mode=2; start_sequence_error=0; else if(bit_counter==2 && sampled_avlink_in==0) mode=3; start_sequence_error=0; else if(bit_counter>=3 && mode==INVALID) mode=INVALID; start_sequence_error=1; Figure 127: Pseudo C Code for Mode Detection 13.8 ESC/DIR Bit Validation The receiver performs optional ESC/DIR bit validation for the mode 0 header. This option is set by setting the AVL_MODE00_HEADER_VALIDATE bit in the memory.

  • Page 374: Interrupts

    ADV7604 14 Interrupts 14.1 Interrupts The ADV7604 has a comprehensive set of interrupt registers located in the IO Map. Two pins, INT1 and INT2, can be configured to output an interrupt signal. The INT2_EN bit in the IO Map must be configured accordingly in order to output INT2. INT2_EN, IO Map, Address 0x41, [2] Function INT2_EN...

  • Page 375: Interrupt Drive Level

    ADV7604 Note: When the active until cleared interrupt duration is selected and the event that caused an interrupt ends, the interrupt persists until it is cleared or masked. 14.1.2 Interrupt Drive Level The drive level of INT1 and INT2 can be programmed via the INTRQ_OP_SEL[1:0] and INTRQ2_OP_SEL[1:0] registers.

  • Page 376: Hdmi Interrupts Validity Checking Process

    ADV7604 Table 88: Interrupt Functions Available in ADV7604 Interrupt Register Location Description Interrupt Status 1 IO Map, Address 0x43 CP interrupt status for SSPD, and STDI and Macrovision Pulse detection Interrupt Status 2 IO Map, Address 0x48 CP interrupt status for Macrovision AGC detection, CGMS and manual interrupt Interrupt Status 3...

  • Page 377: Table 89: Hdmi Interrupts In Io Map Categorized Into Three Groups

    ADV7604 Table 89: HDMI Interrupts in IO Map Categorized into Three Groups Bit Position Register Address 0x61 0x66 0x6B 0x70 0x75 0x7A 0x7F 0x84 *For these status bits to be valid register IO map, address 0x65 bit 7 must be set to 1 14.1.5.1 Group 1 HDMI Interrupts The interrupts listed in Table 90...

  • Page 378: Table 92: Hdmi Interrupts Group 3

    ADV7604 Interrupts IO Map Location AKSV_UPDATE_ST 0x79[5] Note: The TMDS activity on the selected HDMI port is indicated as follows: • TMDS_CLK_A_RAW is set to 1 (IO Map, Address 0x6A[4]) if port A is the active HDMI port • TMDS_CLK_B_RAW is set to 1 (IO Map, Address 0x6A[3]) if port B is the active HDMI port •...

  • Page 379: Storing Masked Interrupts

    ADV7604 Interrupts IO Map Location NEW_MS_INFO_ST 0x75[3] NEW_SPD_INFO_ST 0x75[2] NEW_AUDIO_INFO_ST 0x75[1] NEW_AVI_INFO_ST 0x75[0] FIFO_NEAR_OVFL_ST 0x7A[7] CTS_PASS_THRSH_ST 0x7A[4] CHANGE_N_ST 0x7A[3] PACKET_ERROR_ST 0x7A[2] AUDIO_PCKT_ERR_ST 0x7A[1] NEW_GAMUT_MDATA_ST 0x7A[0] DEEP_COLOR_CHNG_ST 0x7F[7] VCLK_CHNG_ST 0x7F[6] AKSV_UPDATE_ST 0x7F[5] PARITY_ERROR_ST 0x7F[4] NEW_SAMP_RT_ST 0x7F[3] AUDIO_FLT_LINE_ST 0x7F[2] NEW_TDMS_FRQ_ST 0x7F[1] FIFO_NEAR_UFLO_ST 0x7F[0] VS_INF_CKS_ERR_ST 0x84[4]...

  • Page 380: Processing Afe Interrupts

    ADV7604 14.1.7 Processing AFE Interrupts The analog front end (AFE) contains eight trilevel slicers. The inputs to trilevel slicers 1 to 6 are the trilevel signals received on pins TRI1 to TRI6 respectively. Pins HS_IN2 and VS_IN2 can be configured to receive trilevel signals and these inputs are sliced on slicers 7 and 8 respectively. Each trilevel slicer has two digital outputs, one for each slice level.

  • Page 381: Figure 129: Processing Trilevel Interrupts

    ADV7604 Figure 129: Processing Trilevel Interrupts Rev. F August 2010...

  • Page 382: Hardware Design

    ADV7604 15 Hardware Design 15.1 Power Supply Sequence The ADV7604 has six power supplies on two power domains, 1.8V and 3.3V. The following is the power supply sequence recommendation. For individual power supplies on the ADV7604: 1. DVDDIO (3.3V) 2. TVDD (3.3V) 3.

  • Page 383: Register Access And Serial Ports Description

    ADV7604 16 Register Access and Serial Ports Description The ADV7604 has five 2-wire serial (I C compatible) ports: • One main I C port, SDA/SCL, which allows a system I C master controller to control and configure the ADV7604 • Four I C ports, DDC port A, port B, port C and port D which allow an HDMI host to access the internal EDID and the HDCP registers 16.1 Main I...

  • Page 384: Protocol For Main I C Port

    ADV7604 Table 93: Register Maps and I C Addresses Address Programmable Location at which Address Address can be Programmed IO Map 0x40 Not applicable AVLink Map 0x84 IO Map, Register 0xF3 CEC Map 0x80 IO Map, Register 0xF4 InfoFrame Map 0x7C IO Map, Register 0xF5 ESDP Map...

  • Page 385: Ddc Ports

    ADV7604 • In read mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge. This indicates the end of a read. A no acknowledge condition is where the SDA line is not pulled low on the ninth pulse. •...

  • Page 386: I 2 C Protocols For Access To Hdcp Registers

    ADV7604 Figure 76: Current Address Read Sequence 16.2.2 I C Protocols for Access to HDCP Registers An I C master connected on a DDC port can access the internal EDID using the following protocol: • Write sequence, as defined in Section 16.1.2 •...

  • Page 387: Ddc Port C

    ADV7604 Figure 134: Internal E-EDID and HDCP Registers Access from Port B Refer to the High-bandwidth Digital Content Protection (HDCP) System Specifications for detailed information on the HDCP registers. 16.2.5 DDC Port C The DDC lines of the HDMI port C comprise the DDCC_SCL and DDCC_SDA pins. An HDMI host connected to the DDC port C accesses the internal E-EDID at address 0xA0 in read only mode, and the HDCP registers at address 0x74 in read/write mode (refer to Figure...

  • Page 388: Figure 136: Internal E-Edid And Hdcp Registers Access From Port D

    ADV7604 Internal E-EDID HDCPRegisters SA: 0xA0 SA: 0x74 DDCD_SCL DDCD_SDA Figure 136: Internal E-EDID and HDCP Registers Access from Port D Refer to the High-bandwidth Digital Content Protection (HDCP) System Specifications for detailed information on the HDCP registers. Rev. F August 2010...

  • Page 389: Pcb Layout Recommendations

    ADV7604 Appendix A PCB Layout Recommendations The ADV7604 is a high precision, high speed, mixed signal device. It is important to have a well laid out PCB board, in order to achieve the maximum performance from the part. The following sections are a guide for designing a board using the ADV7604.

  • Page 390: Hdmi Inputs

    ADV7604 Figure 137: Recommended Power Supply Decoupling It is particularly important to maintain low noise and good stability of the PVDD (the clock generator supply). Abrupt changes in the PVDD can result in similarly abrupt changes in sampling clock phase and frequency. This can be avoided by careful attention to regulation, filtering, and bypassing.

  • Page 391: Digital Inputs

    ADV7604 close as possible to the ADV7604 pins and the trace impedance for these signals should match that of the termination resistors selected. If possible, the capacitance that each of the digital outputs drives should be limited to is less than 15 pF.
  • Page 392 ADV7604 • Use a parallel-resonant crystal. • Know the C for the crystal part number selected. The value of capacitors C1 and C2 load must be matched to the C for the specific crystal part number in the user’s system. load To find C1 and C2, use the following formula: C1 = C2 = 2(C...

  • Page 393: Table 94: Recommended Configuration For Unused Pins

    ADV7604 Appendix B Recommended Configuration for Unused Pins Table 94: Recommended Configuration for Unused Pins Mnemonic Function DGND Connect this pin to ground RXD_5V If RXA_5V, RXB_5V, RXC_5V and RXD_5V are not used, float RXD_5V and set DIS_CABLE_DET_RST to 0. if RX_A_5V is not used but RXA_5V, RXB_5V or RXC_5V are used, float RXD_5V.
  • Page 394 ADV7604 Mnemonic Function DGND Connect this pin to ground DVDDIO This pin is always connected to the Digital I/O supply voltage (3.3 V). Float this pin. Float this pin. Float this pin. Float this pin. Float this pin. RXD_1- Float this pin. RXD_1+ Float this pin.
  • Page 395 ADV7604 Mnemonic Function Float this pin. Float this pin. RXD_C- Float this pin. RXD_C+ Float this pin. DGND Connect this pin to ground DDCD_SCL Connect this pin to ground via a 10k ohm resistor. This pin is always connected to the I2C clock line of a control processor.
  • Page 396 ADV7604 Mnemonic Function DGND Connect this pin to ground DGND Connect this pin to ground DGND Connect this pin to ground DVDD This pin is always connected to the Digital supply voltage (1.8 V). DVDD This pin is always connected to the Digital supply voltage (1.8 V).
  • Page 397 ADV7604 Mnemonic Function TVDD This pin is always connected to the Terminator supply voltage (3.3 V). TVDD This pin is always connected to the Terminator supply voltage (3.3 V). CVDD This pin is always connected to the Comparator supply voltage (1.8 V). PVDD This pin is always connected to the PLL supply voltage (1.8 V).
  • Page 398 ADV7604 Mnemonic Function DDCA_SCL Connect this pin to ground via a 10k ohm resistor. AGND Connect this pin to ground AGND Connect this pin to ground AGND Connect this pin to ground AGND Connect this pin to ground RXB_C- Float this pin. RXB_C+ Float this pin.
  • Page 399 ADV7604 Mnemonic Function AVDD This pin is always connected to the Analog supply voltage (1.8 V). TRI2 Float this pin. SYNC2 Float this pin. AVDD This pin is always connected to the Analog supply voltage (1.8 V). AIN2 Float this pin. TVDD This pin is always connected to the Terminator supply voltage (3.3 V).

  • Page 400: Recommended Configuration For Unused Pins

    ADV7604 Appendix C Package Outline Drawing 260-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-260-1) Dimensions shown in millimeters 15.10 A1 BALL 15.00 SQ CORNER A1 BALL 14.90 CORNER 13.60 BSC SQ 0.80 TOP VIEW BOTTOM VIEW DETAIL A 1.50 1.11 1.36 1.01...

  • Page 401: List Of Figures

    ADV7604 List of Figures Figure 1: Field Description Format......................................11 Figure 2: Functional Block Diagram ......................................17 Figure 3: ADV7604 Pin Configuration....................................18 Figure 4: Using +5 V from HDMI Source to Provide Supplies in Power-down Mode 0 ......................30 Figure 5: Hardware Configuration Recommended When PWRDNB Pin Required to Enter Power-down Mode 0.............31 Figure 6: Synchronization Path .......................................43 Figure 7: Spreadsheet Screen Shot......................................57 Figure 8: Video Signal Path to ADCs .....................................65...
  • Page 402 ADV7604 Figure 74 AV Code Output Options (CP).....................................244 Figure 75: CP DATA Path Channel A (Y) for Analog Mode ..............................246 Figure 76: CP Data Path Channel B/C (UV) for Analog Mode ............................247 Figure 77: CP Data Path Channel A/B/C (RGB) for Analog Mode.............................248 Figure 78: CP Data Path Channel A (Y) for HDMI Mode..............................249 Figure 79: CP Data Path Channel B/C for HDMI Mode..............................250 Figure 80: Syncs Extracted by ESDP Section ..................................251...

  • Page 403: List Of Tables

    ADV7604 List of Tables Table 1: Pin Function Descriptions......................................18 Table 2: Pin Checker Values Corresponding to Output Pins ..............................47 Table 3: Primary Mode and Video Standard Selection ................................49 Table 4: V_FREQ[2:0] Description ......................................53 Table 5: Recommended Settings for HDMI Inputs ................................55 Table 6: Sub Functions of OP_FORMAT_SEL[7:0] ................................58 Table 7: OP_FORMAT_SEL[7:0] Modes....................................59 Table 8: ADC Input Muxing ........................................67...
  • Page 404 ADV7604 Table 73: Ancillary Data in Byte Output Format .................................334 Table 74: Structure of VBI Data Words in Ancillary Stream ..............................335 Table 75: Framing Code Sequence for Different VBI Standards............................336 Table 76: Total User Data Words for Different VBI Standards............................337 Table 77: VITC Readback Registers.....................................347 Table 78: VDP_GS_VPS_PDC_UTC_CGMSTB_DATA Readback Registers .........................348 Table 79: VDP_CGMS_TYPEB_DATA Readback Registers ............................350...

  • Page 405: List Of Equations

    ADV7604 List of Equations Equation 1: HSync to TLLC Frequency ....................................45 Equation 2: TMDS Frequency in MHz (Measured After TMDS PLL) ..........................112 Equation 3: TMDS Frequency in MHz (Measured Before TMDS PLL)..........................115 Equation 4: Unit Time of Horizontal Filter Measurements..............................126 Equation 5: Relationship Between MCLKOUT, MCLKFS_N, and f ..........................138 Equation 6: z-Transform of 19-Tap Decimation Filter.................................195...

  • Page 406: Document Revision History

    ADV7604 Document Revision History Revision Date Changes Rev. 0 09/2008 Initial Rev A 10/2008 Section 1.6 Added the ECT and EOM acronyms Section 1.7 Added four new references from CENELEC Section 3.1 Updated the description of IDENT register Section 3.2.1.1 This section has been reviewed to clarify the function and use of power-down mode 0 Section 3.2.1.2...
  • Page 407 ADV7604 Revision Date Changes Section 7.16.2 Corrected the location of the FIFO status registers Section 7.18.7 Corrected the name of CS_COPYRIGHT_FORCE register to CS_COPYRIGHT_MANUAL. Section 7.19.1.2 The description of the registers listed in this section has been revised. Section 7.20.1.2 Corrected ‘BCAPS[0] to ‘BCAPS[5]’.
  • Page 408 ADV7604 Revision Date Changes RevD 03/09 Updated section 3.2.1.1 – Power-down Mode 0 Updated bullet points in section 7.9 Updated bullet points in section 7.15.1 Updated bullet points in section 7.15.2 Added final bullet point in section 7.16.12 Added final bullet point in section 7.16.12.2 Updated figure 50 Corrected register address in section 7.19.1.1 Corrected issues in section 7.19.1.2...
  • Page 409 ADV7604 Revision Date Changes TRI7 and TRI8 functions corrected in Section 6.6 Note added to Section 8.5 on brightness control Corrected CLMP_A and CLMP_BC values in Section 10.2 Updated 7.20.1.3 KSV_LIST_READY meaning TEST1 and TEST2 connections clarified Rev. F August 2010...

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