Digital Synthesizer Controls; Clock Generation For Analog Cp Control - Analog Devices Advantiv ADV7604 Hardware Manual

INV_SYNC_OUT_POL, IO Map, Address 0x06, [4]
INV_SYNC_OUT_POL controls the polarity of the SYNC_OUT output signal. This control is only
valid when the ADV7604 outputs a CSync on the SYNC_OUT, i.e. when the part is not configured
in power-save mode.
Function
INV_SYNC_OUT_
POL
0
1
3.6

Digital Synthesizer Controls

The ADV7604 features two digital encoder synthesizers that generate the following clocks:
• Video DPLL:
This clock synthesizer generates an ADC sampling clock/pixel clock for analog, DVI, and
HDMI inputs. For analog input, the video DPLL locks when it has received a horizontal
synchronization with 128 consistent periods. For DVI/HDMI input, the video DPLL locks
within 128 TMDS clock periods after the TMDS PLL has locked.
• Audio DPLL:
This clock synthesizer generates an audio master clock HDMI inputs.
The audio PLL locks within two periods of the audio sampling clock after the TMDS PLL
has locked and when the part has received valid ACR packets.
3.6.1

Clock Generation for Analog CP Control

PLL_DIV_RATIO is automatically decoded from the programmed
VID_STD[5:0] registers.
PLL_DIV_RATIO[12:0]
PLL_DIV_MAN_EN, IO Map, Address 0x16, [7]
Function
PLL_DIV_MAN_E
N
0
1
Rev. F August 2010
Description
Does not invert SYNC_OUT output polarity
Inverts SYNC_OUT output polarity
PLL_DIV_RATIO can also be manually programmed via registers
and PLL_DIV_MAN_EN
Description
Synthesizer feedback value derived from
VID_STD[5:0]
Uses PLL_DIV_RATIO[12:0] as the multiplying factor between HSync
and LLC clocks
PRIM_MODE[3:0]
in the IO Map.
PRIM_MODE[3:0]
44
ADV7604
and
and