7.4.2
Structure of Internal E-EDID for Port A
The internal E-EDID is enabled on port A by setting
internal E-EDID that is accessible on the DDC line of port A is shown in
The image of the internal E-EDID that is accessed on the DDC bus of port A corresponds to the data
image contained in the internal EDID RAM.
Notes:
• After
EDID_A_ENABLE
four checksums of the E-EDID image for port A and updates the internal RAM address
locations 0x7F, 0xFF, 0x17F, and 0xFF in the internal EDID RAM with the computed
checksums.
• After power up, the ADV7604 E-EDID controller sets all bytes in the internal EDID RAM to
0. Since this operation takes less than 1 ms, it is recommended to wait for at least 1 ms
before initializing the EDID Map with E-EDID.
• When internal E-EDID is enabled on port A, the Hot Plug should not be asserted until the
EDID Map has been completely initialized with E-EDID.
• The internal E-EDID can be accessed in read-only mode through the DDC interface at the I
address 0xA0.
• The internal E-EDID can be accessed in read/write mode through the general I
the EDID Map I
Rev. F August 2010
Port A E-EDID Structure
0x1FF
0x180
0x17F
0x100
0xFF
0x80
0x7F
0x00
Figure 23: Port A E-EDID Structure and Mapping
is set to 1, the ADV7604 EDID/Repeater controller calculates the
2
C address.
EDID_A_ENABLE
Block 2 Checksum
0x1FE
Block 3
Block 2 Checksum
0x17E
Block 2
Block 1 Checksum
0xFE
Block 1
Block 0 Checksum
0x7E
Block 0
101
ADV7604
to 1. The structure of the
Figure
23.
2
C interface at
2
C
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