Clamp Control; Figure 107: External Clock And Clamp Mode Block Diagram - Analog Devices Advantiv ADV7604 Hardware Manual

10.16.2 Clamp Control

Figure 107 shows the operational block diagram for external clock and clamp mode.
External Clock
External Clamp

Figure 107: External Clock and Clamp Mode Block Diagram

The ADV7604 clamps video signals using the following two clamping controls:
• Analog Voltage Clamp (ANVC)
This changes the charge on the input coupling capacitor to adjust the DC level of the video
signal to within the range of the ADC. This clamp brings the input signal to approximately
the correct level.
• Digital Fine Clamp (DFC)
This accurately sets the black level of the video. The signal is measured at a time when the
level is known during horizontal blanking and any clamp value on the video is calculated.
This clamp is then digitally subtracted from the video signal, so that the black level is at
exactly the desired value.
These two clamp modes function together provide a digital output at an exactly predictable level.
When external clamp mode is chosen, both of these clamp modes are controlled by the signal applied
to the clamp pin.
Rev. F August 2010
clamp
ADC0
clamp ADC1
ADC2
clamp
ANVC
0
Conrol
ANVC Control
1
Polarity
Control
EXT_VCLMP_POS_EDGE_SEL
EXT_VCLMP_REGEN
DPP_BYPASS_EN
DPP Block
0
1
DFC
Conrol
PRIM_MODE [3:0]
Digital Counter
VID_STD [4:0]
CP_DFC_POS_START [13:0]
CP_ANVC_POS_DURATION [7:0]
CP_ANVC_POS_START [13:0]
EXT_VCLMP_REGEN_MODE
314
Component Processor
Video
Enhancement
Sync
Control
ADV7602
ADV7604
Digital Data
HS/CS
VS/FIELD