System Delay In Adv7604; Figure 109: System Delay In Adv7604 - Analog Devices Advantiv ADV7604 Hardware Manual

Function
CP_DFC_POS_ST
ART[12:0]
x xxxx xxxx xxxx
Notes:
• When CP_DFC_POS_START[12:0] is set to 0x0000, the ADV7604 forces ANVC position
control with an automatic value of 34 external clock cycles after the selected (set by
EXT_VCLMP_POS_EDGE_SEL bit) active clamp pulse edge.
• CP_DFC_POS_START[12:9] (MSB bits of CP_DFC_POS_START[12:0] is active only for
the external clock and clamp mode) also has an effect on the internal clock and clamp mode
and may need to be programmed when the user is in auto graphics mode. Refer to
Section 10.15

10.16.4 System Delay in ADV7604

Figure 109 illustrates the system delay present in the external clock and clamp mode for each
regenerated ANVC and the DFC being applied to the incoming video signal.
External Clock
0
External Clamp
1
Table 65 lists the clock cycle delays present in different operation modes.
Rev. F August 2010
Description
13-bit position control for DFC start positioning in regeneration mode
for the further details.
AFE Delay Block (A)
clamp
ADC0
clamp ADC1
ADC2
clamp
ANVC
Conrol
ANVC Control
Polarity Digital Counter
Control

Figure 109: System Delay in ADV7604

DPP Block
0
1
DFC
Conrol
320
CP Delay Block (B)
Component Processor
Digital Data
Video
Enhancement
HS/CS
Sync
VS/FIELD
Control
ADV7604