Standard Detection And Identification - Analog Devices Advantiv ADV7604 Hardware Manual

SSPD_RSLT_CHNGD_CH2_ST , IO Map, Address 0x5C, [4]
Function
SSPD_RSLT_CHNGD_CH
2_ST
0
1
SSPD_RSLT_CHNGD_CH2_RAW , IO Map, Address 0x5B, [4]
Function
SSPD_RSLT_CHNGD_CH
2_RAW
0
1

10.8.2 Standard Detection and Identification

As shown in Figure 68, the two synchronization processing channels also contain Standard
Detection and Identification (STDI) blocks. These monitor the synchronization signals to determine
the video input standard.
The STDI blocks perform four key measurements:
• Block Length CHx_BL[13:0]
This is the number of 28.6363 MHz clock cycles (XTAL frequency) in a block of eight
lines. From this, the time duration of one line can be concluded.
• Line Count in Field CHx_LCF[10:0]
The CHx_LCF[10:0] readback value is the number of lines between two VSyncs, that is,
over one field measured by channel x.
• Line Count in VSync CHx_LCVS[4:0]
The LCVS[4:0] readback value is the number of lines within one VSync period.
• Field Length CHx_FCL[12:0]
This is the number of 28.6363 MHz clock cycles in a 1/256
Rev. F August 2010
Description
No change in synchronization input to SSPD section of
synchronization channel 2.
Interrupt generated for SSPD_RSLT_CHNGD_CH2_ST after
SSPD_RSLT_CHNGD_CH2_RAW changed. Bit is cleared by
setting SSPD_RSLT_CHNGD_CH2_CLR (IO Map, Address
0x5D[4]) to 1.
Note that SSPD_RSLT_CHNGD_CH1_ST interrupt is enabled:
• By setting SSPD_RSLT_CHNGD_MB1 (IO Map, Address
0x5F[4]) for INT1
• By setting SSPD_RSLT_CHNGD_MB2 (IO Map, Address
0x5E[4]) for INT2
Description
No change in synchronization input to SSPD section of
synchronization channel 2
Set to 1 for 15 crystal clock period if a change occurs in any of
these flags:
• CH1_VS_ACT, CP Map, Address 0x42[6]
• CH1_CUR_POL_VS, CP Map, Address 0x42[5]
• CH1_HS_ACT, CP Map, Address 0x42[4]
• CH1_CUR_POL_HS, CP Map, Address 0x42[3]
267
th
of a field. Alternately, this
ADV7604