Power-Save Mode - Analog Devices Advantiv ADV7604 Hardware Manual

POWER_DOWN, IO Map, Address 0x0C, [5]
Function
POWER_DOWN
0
1
The effect of the pin PWRDNB can be disabled by setting DIS_PWRDNB to 1. When this is done,
the part is in power down mode 1 if:
•
POWER_DOWN
• The CEC section is enabled by setting
enabled by setting bit
DIS_PWRDNB, HDMI Map, Address 0x48, [7]
Function
DIS_PWRDNB
0
1
3.2.2

Power-Save Mode

The PWR_SAVE_MODE
disables selected blocks of the ADV7604, with the exception of the analog synchronization stripper
and some auxiliary digital blocks. Using the power-save mode, the ADV7604 still outputs
synchronization information derived from the synchronization input pins (refer to Section 3.2).
Power-save mode can be used to implement an activity detection feature whereby an external
device monitors the synchronization information as output from the ADV7604 while the rest of the
IC is still in power-down mode, thus conserving energy. The part will leave the power-save mode if
the PWR_SAVE_MODE
Notes:
• If
POWER_DOWN
POWER_SAVE_MODE
• The XTAL clock is powered down in the following sections:
STDI blocks
SSPD blocks
Free run synchronization generation block
2
I C sequencer block, which is used for the configuration of the gain, clamp, and offset
CP section
DPP section
• The internal EDID is functional in power-save mode.
Rev. F August 2010
Description
Power-down disabled
Power-down enabled
is set to 1
AVLINK_POWER_UP
Description
Does not disable the effect of pin PWRDNB
Disables the effect of pin PWRDNB
bit allows the user to set the ADV7604 into a power-save mode that
bit is set to 0 or if the overall part is reset using the RESET pin.
and POWER_SAVE_MODE
takes priority.
CEC_POWER_UP to 1 or the AV.link section is
to 1
are set simultaneously,
32
ADV7604