External Sync And Sync From Hdmi Section; Figure 82: External/Hdmi Syncs Routing To Cp Section - Analog Devices Advantiv ADV7604 Hardware Manual

SYNC_CH2_EMB_SYNC_SEL[1:0] , Channel 2 Embedded Sync Selection, IO Map, Address
0x08, [1:0]
Function
SYNC_CH2_EMB_
SYNC_SEL[1:0]
00
01
10
11

10.7.3 External Sync and Sync from HDMI Section

The CP section can receive syncs from the external HSync, VSync and CSync inputs or from the
HDMI section, as shown in
embedded sync signals, EMB_SYNC_1 and EMB_SYNC_2, which are output by the sync slicers.
PRIM_MODE[2]
HS/CS_IN1
HS/CS_IN2
HDMI HS
SYNC_CH1_HS_SEL[1:0]
SYNC_CH2_HS_SEL[1:0]
PRIM_MODE[2]
VS_IN1
VS_IN2
HDMI VS
SYNC_CH1_VS_SEL[1:0]
SYNC_CH2_VS_SEL[1:0]
Rev. F August 2010
Description
EMB_SYNC_SEL_2
EMB_SYNC_SEL_1
Reserved
Reserved
Figure 82. Note also that
0
1 00
01
10 HS/CS 1
11
HS/CS 2
00
01
10
11
EMB_SYNC_1
0
1 00 EMB_SYNC_2
01
10
11
00 VS 1
01
10 VS 2
11

Figure 82: External/HDMI Syncs Routing to CP Section

Figure 82 shows the routing of the internal
HS/CS 1
HS/CS1_GR SSPD 1
VS1
VS1_GR
POLARITY
EMB_SYNC_1 CORRECTION
EMB_SYNC_1_GR
STDI 1 HS_GR_PC
EMBEDDED_
VS_GR_PC
SYNC_MODE
STDI 2 HS_GR_PC
EMBEDDED_
VS_GR_PC
SYNC_MODE
HS/CS2
HS/CS2_GR SSPD 2
VS2
VS2_GR
POLARITY
EMB_SYNC_2 CORRECTION
EMB_SYNC_2_GR
DIG_SYNC_DEGLITCH_REDUCE
DIG SYNC DEGLITCH REDUCE MAN
253
SEL_SYNC_CH1_AUTO
SYNC_CH1_PRIORITY
CH1_SYNC_SRC[1:0]
CH1_SSPD_CONT
CH1_TRIG_SSPD
CH1_POL_MAN_EN
CH1_POL_HSCS
CH1_POL_VS
TO SYNC/ESDP MUX
HS_PC
HS1_PC
VS1_PC
HS2_PC
VS2_PC
TO SYNC/ESDP MUX
VS_PC
TO SYNC/ESDP MUX
EMBEDDED_
SYNC_MODE
CH2_SYNC_SRC[1:0]
CH2_SSPD_CONT
CH2_TRIG_SSPD
CH2_POL_MAN_EN
CH2_POL_HSCS
CH2_POL_VS
ADV7604