Antiglitch Filter Module; Typical Operation Flow; Initializing Cec Module - Analog Devices Advantiv ADV7604 Hardware Manual

CEC_CLOCK_DIVIDER[7:0], Clock Divider Value , CEC Map, Address 0x2A, [7:0]
Function
CEC_CLOCK_DIV
IDER[7:0]
xxxxxxxx
00111110

12.5 Antiglitch Filter Module

This module is used to remove the glitches in the CEC bus in order to make the CEC input signal
cleaner before it enters the CEC module. The glitch filter is programmable through the
CEC_GLITCH_FILTER_CTRL
less than the CEC_GLITCH_FILTER_CTRL
and consequently removed by the filter. Correspondingly, there is a
+ 1 number of clock delays introduced by the anti glitch filter.
CEC_GLITCH_FILTER_CTRL[5:0], Glitch Filter Control , CEC Map, Address 0x2B, [5:0]
Function
CEC_GLITCH_FIL
TER_CTRL[5:0]
xxxxxx
000111

12.6 Typical Operation Flow

This section describes the algorithm that should be implemented in the host processor controlling the
CEC module.

12.6.1 Initializing CEC Module

Figure 117 shows the flow that can be implemented in the host processor controlling the ADV7604
in order to initialize the CEC module.
Rev. F August 2010
Description
CEC clock is the Xtal clock divided by value set in this register
Default value
registers. The register value indicates that the pulse whose width is
Description
Pulse within number of Xtal clock cycles that must be recognized as a
glitch
Default value
number of clock cycles must be recognized as a glitch
359
CEC_GLITCH_FILTER_CTRL
ADV7604