Table of Contents
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Preliminary Technical Data
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
ADM1060 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ADM1060 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Powering the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Programmable Supply Fault Detectors (SFD's) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SFD Comparator Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bipolar SFD's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SFD Fault Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Glitch Filtering on the SFD's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Programming the SFD's on the SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SFD Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SFD Register Bitmaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bipolar Supply Fail Detect (BSnSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
High Voltage Supply Fault Detect (HVSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Positive Voltage Supply Fault Detect (PSnSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Watchdog Fault Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General Purpose Inputs (GPI's) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Logic State of the GPI's (and other Logic Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Programmable Logic Block Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PLBA Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PLBA Register Bitmaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Programmable Delay Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Programmable Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fault/Status Reporting on the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Fault Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuuration Download at Power- Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Updating the Configuration of the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Internal Registers of the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SMBus Protocols for RAM and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ADM1060 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ADM1060 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Applications Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
REV. PrJ 11/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRELIMINARY TECHNICAL DATA
ADM1060 TABLE OF CONTENTS
Communications System
Supervisory/Sequencing Circuit
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
ADM1060
© Analog Devices, Inc., 2002
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Summary of Contents for Analog Devices ADM1060
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Page 1: Table Of Contents
Updating the Configuration of the ADM1060 ........ -
Page 2: Features
Programmable Logic Block Array. This is A P P L I C A T I O N S the logic core of the ADM1060. It is comprised of 9 Central Office Systems macrocells, one for each PDO. -
Page 3: Adm1060 Functional Block Diagram
Internal 5.5V supply VCCP REGULATED Data, Address and 5.5V SUPPLY Write Enable Buses CHARGE PUMP to store control information local to functions V DD ARBITRATOR EEPROM DEVICE SMBus INTERFACE CONTROLLER ADM1060 FUNCTIONAL BLOCK DIAGRAM REV. PrJ 11/02 – 3 –... -
Page 4: Specifications
PRELIMINARY TECHNICAL DATA ADM1060–SPECIFICATIONS (VH=4.5V to 14.4V, VPn = 3.0V to 6.0V = -40 C to 85 C, unless otherwise noted.) Parameter Units Test Conditions/Comments POWER SUPPLY ARBITRATION VDDCAP Any VPn>=3.0V VH>=4.5V 4.75 Any VPn=6.0V 4.75 VH=14.4V POWER SUPPLY Supply Current, I VDDCAP=4.75V, no PDO FET... - Page 5 PRELIMINARY TECHNICAL DATA ADM1060–SPECIFICATIONS (VH=4.5V to 14.4V, VPn = 3.0V to 6.0V = -40 C to 85 C, unless otherwise noted.) Parameter Units Test Conditions/Comments PROGRAMMABLE DRIVER OUTPUTS High Voltage (Charge Pump) Mode (PDO’s 1 to 4) Output Impedance, R 10.5...
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Page 6: Pin Function Description
Reservoir Capacitor for Central Charge Pump. This charge pump powers all of the internal circuits of the ADM1060 and provides the first stage in the tripler circuits used to produce 12V of gate drive on PDO’s 1- 4. High Voltage Supply Input. 2 input ranges. A supply of between 2V and 6V or between 4.8V and 14.4V can be applied to this pin. -
Page 7: Adm1060 Inputs
Also, the minimum supply of 3.0V must appear on type can be selected at a time. one of the VPn pins in order to power up the ADM1060 correctly. A supply of no less than 4.5V can be used on An Undervoltage fault is detected by comparing the input VH. -
Page 8: Sfd Comparator Hysteresis
15.6mV when the SFD’s are in negative mode. Note that the bi- 1V to 3V 7.8mV polar SFD’s cannot be used to power the ADM1060, even 0.6V to 1.8V 4.7mV if the voltage on VBn is positive. SFD FAULT TYPES Table 1. -
Page 9: Programming The Sfd's On The Smbus
The tables show how to set up UV threshold, UV hyster- esis, OV threshold, OV hysteresis, glitch filtering and fault type for each of the SFD’s on the ADM1060. T GF T GF... - Page 10 PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 INPUTS TABLE 2. LIST OF REGISTERS FOR THE SUPPLY FAULT DETECTORS (Contd.) Table Name Default Description Address Power On Value PS2UVTH Undervoltage Threshold for PS2SFD PS2UVHYST Digital Hysteresis on UV threshold for PS2SFD PS2SEL Glitch filter, Range and Fault Type select for PS2SFD...
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Page 11: Sfd Register Bitmaps
PRELIMINARY TECHNICAL DATA ADM1060 INPUTS ADM1060 SFD REGISTER BITMAPS BIPOLAR SUPPLY FAIL DETECT (BSnSFD) REGISTERS TABLE 3. REGISTER A0H,A8H BSnOVTH (POWER- ON DEFAULT FFH) Name Description OV7-OV0 R / W 8 bit digital value for overvoltage threshold on BSn SFD. -
Page 12: High Voltage Supply Fault Detect (Hvsfd) Registers
PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 INPUTS HIGH VOLTAGE SUPPLY FAULT DETECT (HVSFD) REGISTERS TABLE 8. REGISTER B0H HSOVTH (POWER- ON DEFAULT FFH) Name Description OV7-OV0 R / W 8 bit digital value for overvoltage threshold on HV SFD. TABLE 9. REGISTER B1H HSOVHYST (POWER- ON DEFAULT 00H) -
Page 13: Positive Voltage Supply Fault Detect (Psnsfd) Registers
PRELIMINARY TECHNICAL DATA ADM1060 INPUTS ADM1060 POSITIVE VOLTAGE SUPPLY FAULT DETECT (PSNSFD) REGISTERS TABLE 13. REGISTER B8H,C0H,C8H,D0H PSNOVTH (POWER- ON DEFAULT FFH) Name Description OV7-OV0 R / W 8 bit digital value for overvoltage threshold on PSn SFD. TABLE 14. REGISTER B9H,C1H,C9H,D1H PSnOVHYST (POWER- ON DEFAULT 00H) -
Page 14: Watchdog Fault Detector
ADM1060 INPUTS WATCHDOG FAULT DETECTOR can also be inverted, if required (eg) if a high- low- high The ADM1060 has a Watchdog Fault Detector. This can pulse was required by a processor to reset. Thus, a fault be used to monitor a processor clock to ensure normal on the watchdog can be used to generate a pulsed or operation. -
Page 15: General Purpose Inputs (Gpi's)
Manual Resets etc. These signals can be gated with source. The current sources can be connected to the the other inputs supervised by the ADM1060, and used to inputs by progamming the relevant bit in a register control the status of the PDO’s. The inputs can be simply (PDEN). - Page 16 PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 INPUTS TABLE 22. LIST OF REGISTERS FOR THE PULL- DOWN CURRENT SOURCES ON LOGIC INPUTS Table Name Default Description Address Power On Value PDEN Setup of the Pull- down current sources on all logic inputs. Pulls the selected input to GND TABLE 23.
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Page 17: Programmable Logic Block Array
Array (PLBA). This block is the logical core of the device. The PLBA (and the PDBs- see next section) is what provides the sequencing function of the ADM1060. The assertion of the 9 Programmable Driver Outputs (PDO) is controlled by the PLBA. The PLBA comprises of 9 macrocells, 1 per PDO Channel. - Page 18 PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 LOGIC The diagram shown highlights all 21 inputs to a given function and the register/ bits which need to be set in (ie) Not Connected order to condition the 21 inputs correctly. The diagram only shows function A of Programmable Logic Block 1 (PLB1) but all functions are programmed in the same way.
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Page 19: Plba Register Names
PRELIMINARY TECHNICAL DATA ADM1060 LOGIC ADM1060 PLBA REGISTER NAMES TABLE 27. LIST OF REGISTERS FOR THE PROGRAMMABLE LOGIC BLOCK ARRAY (PLBA) Table Name Default Description Address Power On Value P1PLBPOLA Polarity Sense for all 8 other PLB outputs when used as... - Page 20 PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 LOGIC TABLE 27. LIST OF REGISTERS FOR THE PROGRAMMABLE LOGIC BLOCK ARRAY (PLBA) (Contd.) Table Name Default Description Address Power On Value P2PLBIMKB Ignore Mask for all 8 other PLB outputs when used as inputs to the B function of PLB2 P2SFDPOLB Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to...
- Page 21 PRELIMINARY TECHNICAL DATA ADM1060 LOGIC ADM1060 TABLE 27. LIST OF REGISTERS FOR THE PROGRAMMABLE LOGIC BLOCK ARRAY (PLBA) (Contd.) Table Name Default Description Address Power On Value P4PLBPOLB Polarity Sense for all 8 other PLB outputs when used as inputs to the B function of PLB4...
- Page 22 PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 LOGIC TABLE 27. LIST OF REGISTERS FOR THE PROGRAMMABLE LOGIC BLOCK ARRAY (PLBA) (Contd.) Table Name Default Description Address Power On Value P6WDICFG Polarity Sense and Ignore Mask bits for the pulsed and latched outputs of the watchdog detector when used as...
- Page 23 PRELIMINARY TECHNICAL DATA ADM1060 LOGIC ADM1060 TABLE 27. LIST OF REGISTERS FOR THE PROGRAMMABLE LOGIC BLOCK ARRAY (PLBA) (Contd.) Table Name Default Description Address Power On Value P8GPIIMK Polarity Sense and Ignore Mask bits for all 4 GPI’s when used as inputs to the B function of PLB8...
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Page 24: Plba Register Bitmaps
PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 LOGIC PLBA REGISTER BITMAPS TABLE 28. BIT MAP FOR PnPLBPOLA/PnPLBPOLB REGISTERS (POWER- ON DEFAULT 00H) Name Description POL9-POL1 R / W If high, invert the PLBn input before it is used in function A or B... - Page 25 PRELIMINARY TECHNICAL DATA ADM1060 LOGIC ADM1060 V B 2 V B 2 V B 2 V B 2 V B 2 V B 2 V B 2 V B 2 V B 2 V B 1 V B 1 V B 1...
- Page 26 PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 LOGIC TABLE 33. BIT MAP FOR PNGPIIMK REGISTERS (POWER- ON DEFAULT 00H) Name Description AIMK4-AIMK1 R / W If high, mask the GPIn input before it is used in function A BIMK4-BIMK1 R / W...
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Page 27: Programmable Delay Block
PRELIMINARY TECHNICAL DATA ADM1060 LOGIC ADM1060 PDB INPUT PROGRAMMABLE DELAY BLOCK PROGRAMMED FALLTIME =0 PROGRAMMED RISETIME Each output of the PLBA is fed into a separate Program- PROGRAMMED RISETIME mable Delay Block (PDB). The PDB enables the user to add a delay to the logic block output before it is applied to either a PDO or one of the other PLB’s (the output of a... - Page 28 PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 LOGIC TABLE 36. LIST OF REGISTERS FOR PROGRAMMABLE DELAY BLOCK (PDB) Table Name Default Description Addr. Power On Value P1PDBTIM Delay for PDB1. Delay for rising edge and falling edge pro grammed separately. P2PDBTIM Delay for PDB2. Delay for rising edge and falling edge pro grammed separately.
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Page 29: Programmable Driver Outputs
DSP or other microprocessor), provide enable (enabled by setting bit CFG5 to1). When set in this signals for LDO’s on the supplies that the ADM1060 is mode, the data from the PDB is disabled and the data on supervising etc. - Page 30 PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 OUTPUTS TABLE 38. LIST OF REGISTERS FOR THE PROGRAMMABLE DRIVER OUTPUTS Table Name Default Description Address Power On Value P1PDOCFG Selects the format of the PDO1 output (open drain, open drain with internal pull-up, charge pumped etc.)
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Page 31: Fault/Status Reporting On The Adm1060
LATF1 and LATF2, which the system control- up on VP1. The supply is ramped in and out of this win- ler can read out of the ADM1060 via the SMBus. Each dow, each time reading the contents of LATF1 and bit in the 2 registers (with one important exception, see LATF2. -
Page 32: Status Registers
PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 STATUS/FAULTS those of the fault registers with the exception that the ANYFLT bit cannot be masked. Setting a 1 in the error mask register results in the equivalent bit in the fault reg- ister always remaining at 0, regardless of whether there is a fault on that function or not. - Page 33 PRELIMINARY TECHNICAL DATA ADM1060 STATUS/FAULTS ADM1060 TABLE 43. BIT MAP FOR SFDSTAT REGISTER DAH (POWER- ON DEFAULT 00H) Name Description Reserved Cannot be used VP4FLT If high, then fault (UV, OV or Out- of- Window) has occurred on VP4 input...
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Page 34: Fault Registers
PRELIMINARY TECHNICAL DATA ADM1060 ADM1060 STATUS/FAULTS FAULT REGISTERS TABLE 47. LIST OF FAULT REGISTERS Table Name Default Description Addr. Power On Value LATF1 Fault Status Register for the 7 SFD’s LATF2 Fault Status Register for the 4 GPI’s and the Watchdog Detector TABLE 48. -
Page 35: Mask Registers
PRELIMINARY TECHNICAL DATA ADM1060 STATUS/FAULTS ADM1060 MASK REGISTERS TABLE 50. LIST OF MASK REGISTERS Table Name Default Description Addr. Power On Value ERRMASK1 Error Mask Register for the 7 SFD’s ERRMASK2 Error Mask Register for the 4 GPI’s and the Watchdog Detector TABLE 51. -
Page 36: Configuuration Download At Power- Up
EEPROM into the RAM registers, the user may wish to alter the configuration of functions on the ADM1060 (eg) change the UV or OV limit of an SFD, change the fault output of an SFD, change the timeout of the Watchdog Detector, change the rise time delay of one of the PDO’s etc. - Page 37 This bit self clears (returns to 0) after the download R / W If set high, the ADM1060 will update its configuration in real time as a word is written to a local RAM register via the SMBus...
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Page 38: Internal Registers Of The Adm1060
When writing to download is completed. the ADM1060, the first byte of data is always a register ad- dress, which is written to the Address Pointer Register. IDENTIFYING THE ADM1060 ON THE SMBUS Configuration Registers: Provide control and configuration The ADM1060 has a 7-bit serial bus slave address. - Page 39 PRELIMINARY TECHNICAL DATA PROGRAMMING ADM1060 ADM1060 If the operation is a write operation, the first data byte to assert a STOP condition. In READ mode, the mas- after the slave address is a command byte. This tells the ter device will release the SDA line during the low slave device what to expect next.
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Page 40: Smbus Protocols For Ram And Eeprom
In the ADM1060, the write byte/word protocol is used for In the ADM1060, the send byte protocol is used for two three purposes. purposes. 1. Write a single byte of data to RAM. In this case the 1. -
Page 41: Adm1060 Read Operations
In the case of the cation allows a maximum of 32 data bytes to be sent in ADM1060 this is done by a Send Byte operation to set a a block write. RAM address, or a Write Byte/Word operation to set an 7. -
Page 42: Error Correction
(high). 8. The slave asserts ACK on SDA. 9. The ADM1060 sends a byte count data byte that tells the master how many data bytes to expect. The ADM1060 will always return 32 data bytes (20h), which is the maxi- mum allowed by the SMBus 1.1 specification. -
Page 43: Applications Diagram
VCCP +12V_IN PDO1 PDO2 PDO3 PDO4 ADM1060 PWR_OK PDO5 -5V_IN PDO6 PDO7 GPI1 PDO8 GPI2 GPI3 PDO9 VIN_I/O PWRGD GPI4 VOUT A0 A1 CLKOUT 0.9V_OUT +1.8V VOUT VIN_CORE +3.3V VOUT -5V_OUT Figure 10. ADM1060 Application Diagram REV. PrJ 11/02 –43–... -
Page 44: Register Map
ADM1060 Register Map BLOCK PLB1 P1PLBPOLA P1PLBIMKA P1SFDPOLA P1SFDIMKA P1GPIPOL P1GPIIMK P1WDICFG P1EN P1PLBPOLB P1PLBIMKB P1SFDPOLB P1SFDIMKB P1PDBTIM P1PDOCFG PLB2 P2PLBPOLA P2PLBIMKA P2SFDPOLA P2SFDIMKA P2GPIPOL P2GPIIMK P2WDICFG P2EN P2PLBPOLB P2PLBIMKB P2SFDPOLB P2SFDIMKB P2PDBTIM P2PDOCFG PLB3 P3PLBPOLA P3PLBIMKA P3SFDPOLA P3SFDIMKA P3GPIPOL... -
Page 45: Outline Dimensions
6. Definition of fault/status reporting on the ADM1060 7. Addition of Pull- Up/Down current source on logic inputs 8. Corrected version of how SMBus protocol is implemented on the ADM1060. 9. Inclusion of device ID registers (p.37) REV. PrJ 11/02...
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