Final Sync Muxing Stage - Analog Devices Advantiv ADV7604 Hardware Manual

DIG_SYNC_DEGLITCH_REDUCE_MAN, CP Map, Address 0xF5, [2]
Function
DIG_SYNC_DEGLITCH_R
EDUCE_MAN
0
1
10.7.3.3 Signal Routed to SSPD Blocks
The SSPD block from each synchronization channel receives six input signals, namely HS, HS_GR,
VS, VS_GR, EMB_SYNC, and EMB_SYNC_GR. SSPD analyses the _GR signals to determine
which signals have valid sync information, and will 'correct' the polarity of the syncs. In this
instance, the definition of a 'correct' sync polarity is 'negative going', so for input formats with
positive going syncs, these syncs will be inverted. The outputs from the SSPD section are the signals
whose names end with _PC. These signals are the polarity corrected version of the syncs signals
input to the SSPD sections.
The SSPD block will pass a corrected, registered, glitch rejected HSync and VSync signal to the
STDI block. Note that for embedded sync inputs or external CSync inputs where both HSync and
VSync information are contained in one signal, the same signal will be applied to both inputs of the
STDI block.
The SSPD block will also pass a corrected HS and VS signal to the final mux shown on the right side
of Figure 82, as well as a signal called
source of the HS_PC and VS_PC signals are from an embedded signal or separate signals. These
syncs are polarity corrected but are not XTAL registered, nor are they glitch rejected.
The final mux shown in
information signal) from sync channel 1 and sync channel 2. Various controls exist to select how the
SSPD block works, and which sync channel is passed to the CP core. These controls are described in
detail in Section 10.7.
Note that as stated previously, the syncs signals VS_PC and HS_PC passed to the CP core are
polarity corrected but not XATL registered and glitch rejected. However, internally in the CP core, a
glitch rejection filter is applied which rejects any sync signals less than seven CP clocks in width.
This glitch filter is not controllable.

10.7.4 Final Sync Muxing Stage

Rev. F August 2010
Description
Deglitch filter configured in automatic mode. Deglitch filters
before the SSPD sections automatically remove any sync
signals less than five XTAL clocks wide for component inputs
up to and including 1080i, and sync signals that are less than
two XTAL clocks wide for component input 1080p and
graphics standards.
Deglitch filter configured according to
DIG_SYNC_DEGLITCH_REDUCE.
EMBEDDED_SYNC_MODE
Figure 82 selects between the HSync and VSync (and embedded sync
256
ADV7604
which tells the CP core if the