Interrupt Drive Level; Interrupt Manual Assertion; Multiple Interrupt Events - Analog Devices Advantiv ADV7604 Hardware Manual

Note: When the active until cleared interrupt duration is selected and the event that caused an
interrupt ends, the interrupt persists until it is cleared or masked.

14.1.2 Interrupt Drive Level

The drive level of INT1 and INT2 can be programmed via the INTRQ_OP_SEL[1:0] and
INTRQ2_OP_SEL[1:0] registers.
INTRQ_OP_SEL[1:0] , IO Map, Address 0x40, [1:0]
Function
INTRQ_OP_SEL[1:0]
00
01
10
11
INTRQ2_OP_SEL[1:0] , IO Map, Address 0x41, [7:6]
Function
INTRQ2_OP_SEL[1:0]
00
01
10
11

14.1.3 Interrupt Manual Assertion

It is possible to assert manually the INT1 and INT2 pins by setting MPU_STIM_INT.
MPU_STIM_INTRQ, IO Map, Address 0x40, [2]
Function
MPU_STIM_INT
0
1

14.1.4 Multiple Interrupt Events

If an interrupt event occurs, and then a second interrupt event occurs before the system controller
has cleared or masked the first interrupt event, the ADV7604 does not generate a second interrupt
signal. The system controller should check all unmasked interrupt status bits as more than one may
be active.
Table 88 lists the interrupt registers available and a brief description of their functions. For more
details on the functionality of these interrupt registers, refer to the ADV7604 Software Manual.
Refer to the IO Map section of the ADV7604 Software Manual for details of the CP core interrupts
and HDMI core interrupts. Refer to the AFE Map section of the ADV7604 Software Manual for
details on trilevel synchronization interrupts.
Rev. F August 2010
Selects INT1 output drive level
Open drain
Drives low when active
Drives high when active
Reserved
Selects INT2 output drive level
Open drain
Drives low when active
Drives high when active
Reserved
Description
Does not manually assert INT1 and INT2 pins
Manually asserts INT1 and IN2 pins
375
ADV7604