Audio Dpll - Analog Devices Advantiv ADV7604 Hardware Manual

7.16.1 Audio DPLL

The audio DPLL generates an internal audio master clock with a frequency of 128 times the audio
sampling frequency, usually called fs. The audio master clock is used to clock the audio processing
section.
7.16.1.1 Locking Mechanism
When the upstream HDMI transmitter outputs a stable TMDS frequency and consistent audio clock
regeneration values, the audio DPLL locks within two cycles of the audio master clock after the
following two conditions are met:
• TMDS PLL is locked (refer to VIDEO_PLL_LCK_RAW)
• ADV7604 has received an ACR packet with N and CTS parameters within a valid range
The audio DPLL lock status can be monitored via AUDIO_PLL_LOCKED.
AUDIO_PLL_LOCKED , HDMI Map, Address 0x04, [0]
Function
AUDIO_PLL_LOCKED
0
1
7.16.1.2 ACR Parameters Loading Method
The N and CTS parameters from the ACR packets are used to regenerate the audio clock and are
reloaded into the DPLL anytime they change. The self-clearing bit
means to reset the audio DPLL by forcing a reload of the N and CTS parameters from the ACR
packet into the audio DPLL.
FORCE_N_UPDATE , HDMI Map, Address 0x5A, [0]
Function
FORCE_N_UPDATE
0
1
7.16.1.3 Audio DPLL Coast Feature
The audio DPLL incorporates a coast feature that allows it to indefinitely output a stable audio
master clock when selectable events occur. The coast feature allows the audio DPLL to provide an
audio master clock when the audio processor mutes the audio following a mute condition (refer to
Section 7.16.10). The events that cause the audio DPLL to coast are selected via the coasts masks
listed in Table 16.
Rev. F August 2010
Description
Audio DPLL is not locked
Audio DPLL is locked
Description
Does not force a reload of the ACR parameters N and CTS into
the audio DPLL
Forces a reload of the ACR parameters N and CTS into the audio
DPLL
132
FORCE_N_UPDATE
ADV7604
provides a