Appendix A
PCB Layout Recommendations
The ADV7604 is a high precision, high speed, mixed signal device. It is important to have a well
laid out PCB board, in order to achieve the maximum performance from the part. The following
sections are a guide for designing a board using the ADV7604.
Analogue Interface Inputs
It is extremely important to use the following layout techniques on the graphics inputs.
The trace length running into the graphics inputs should be minimized in length. This is
accomplished by placing the ADV7604 as close as possible to the graphic connector. Long input
trace lengths are undesirable because they pick up more noise from the board and other external
sources.
The voltage divider 36 ohm/39 ohm, which acts as a 75 ohm termination, should be placed as close
as possible to the ADV7604 chip. Any additional trace length between the termination resistors and
the input of the ADV7604 increases the magnitude of reflections, which corrupts the graphics signal.
75 ohm matched impedance traces should be used. Trace impedances other than 75 ohms also
increase the chance of reflections.
The ADV7604 has high input bandwidth. While this is desirable for acquiring a high resolution PC
graphics signal with fast edges, it means that it also captures any high frequency noise that is
present. Therefore, it is important to reduce the amount of noise that is coupled to the inputs. The
user should avoid running any digital traces near the analog inputs and insure signal traces do not
run too close together to avoid crosstalk.
The nongraphics input should also receive care when being routed on the PCB. Again, track lengths
should be kept to a minimum and 75 ohm traces impedances should be used where possible.
The following routing is strongly recommended:
• RGB Graphics − Ain 7, 8, 9
• Component 1 − Ain10, 11, 12
• Component 2 − Ain 4, 5, 6
• SCART (RGB) − Ain 1, 2, 3
Power Supply Bypassing
It is recommended to bypass each power supply pin with a 0.1 uF and a 10 nF capacitor where
possible. The fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin.
The bypass capacitors should be physically located between the power plane and the power pin.
Current should flow from the power plane to the capacitor to the power pin. The power connection
should not be made between the capacitor and the power pin. Generally, the best approach is to
place a via underneath the 100 nF capacitor pads down to the power plane (refer to
Rev. F August 2010
389
ADV7604
Figure
137).
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