Analog Devices Advantiv ADV7604 Hardware Manual page 319

CP_ANVC_POS_START[12:0], CP Map, Address 0xC6, [7:0], Address 0xCA, [7:4], Address
0xC9, [7]
As shown in Figure 107, the start time of the analog voltage clamp relative to the input clamp signal
can be controlled by CP_ANVC_POS_START[12:0] with external clock period accuracy in
regeneration mode. This is the delay in external clock cycles between the selected (set by the
EXT_VCLMP_POS_EDGE_SEL
voltage clamp is applied.
Function
CP_ANVC_POS_S
TART[12:0]
x xxxx xxxx xxxx
Note that when CP_ANVC_POS_START[12:0] is set to 0x0000, the ADV7604 will force ANVC
position control with an automatic value of 10 external clock cycles after the active clamp pulse edge.
CP_ANVC_POS_DURATION[7:0], CP Map, Address 0xC7, [7:0]
As shown in Figure 107, the duration of the analog voltage clamp can be controlled by
CP_ANVC_POS_DURATION[7:0] with external clock period accuracy in regeneration mode. This
represents the duration of the ANVC pulse in external clock cycles.
Function
CP_ANVC_POS_
DURATION[7:0]
xxxx xxxx
Notes:
• When CP_ANVC_POS_DURATION[7:0] is set to 0x0000, the ADV7604 forces ANVC
duration control with an automatic value of 20 external clock cycles after the active clamp
pulse edge.
• CP_ANVC_POS_START[12:9] (MSB bits of CP_ANVC_POS_START[12:0] is active only
for the external clock and clamp mode) also has an effect on the internal clock and clamp
mode and may need to be programmed when the user is in the auto graphics mode. Refer to
Section 10.15
CP_DFC_POS_START[12:0], CP Map, Address 0xC8, [7:0], Address 0xCA, [3:0], Address 0xC9,
[6]
As shown in Figure 107, the start point of the digital fine clamp is controlled with
CP_DFC_POS_START[12:0] with external clock period accuracy in regeneration mode. This is the
delay in external clock cycles between the selected (set by EXT_VCLMP_POS_EDGE_SEL)
leading edge of the external clamp pulse and the time when the digital fine clamp is applied.
The duration of the digital clamp is not programmable; it is fixed at 16 clock cycles. This is required
for the algorithm that measures the digital clamp value to function correctly.
Rev. F August 2010
bit) leading edge of the input clamp signal and the time when the
Description
13-bit position control for ANVC start positioning in regeneration mode
Description
8-bit duration control for ANVC clamping period in regeneration mode
for the further details.
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ADV7604