Output Timing Signals; Table 48: Synchronization Timing Adjustment Controls - Analog Devices Advantiv ADV7604 Hardware Manual

after the ADV7604 adjusts the picture down by four lines to compensate for this four line delay on
output timing. This is typically quite easy for a backend chip to do and results in a stable picture with
correct vertical position.
9.8

Output Timing Signals

Although there are many registers to control ESDP output timing signals, limited programming is
required for most applications supporting standard timing requirements.
As mentioned in Section
DE, Field, V bit, and F bit of SAV/EAV codes) compared with the specification. To maintain correct
picture alignment, it is required that the backend chip after the ADV7604 adjusts the picture down by
four lines to compensate for this four line delay on output timing.
By default, output timing is set up to be correct for SD and ED modes (subject to the four line offset
mentioned previously) and should only be changed to suit any unusual requirements of a backend
chip. The controls listed in
their default positions.
Control
EAV_POS_ADJ[11:0]
SAV_POS_ADJ[11:0]
HS_BEG_ADJ[11:0]
HS_WIDTH[11:0]
DE_H_BEG_ADJ[11:]
DE_H_END_ADJ[11:0]
VSF_H_BEG_ADJ[11:0]
VSF_H_MID_ADJ[11:0]
V_BEG_O_ADJ[5:0]
V_BEG_E_ADJ[5:0]
V_END_O_ADJ[5:0]
V_END_E_ADJ[5:0]
F_TOG_O_ADJ[5:0]
F_TOG_E_ADJ[5:0]
FLD_TOG_O_ADJ[5:0]
FLD_TOG_E_ADJ[5:0]
VS_V_BEG_O_ADJ[5:0]
VS_V_BEG_E_ADJ[5:0]
VS_V_END_O_ADJ[5:0]
Rev. F August 2010
9.7, there is a four line delay on all output vertical timing signals (VSync,
Table 48 allow horizontal and vertical timing signals to be adjusted from

Table 48: Synchronization Timing Adjustment Controls

ESDP Map Address
0x90[3:0], 0x91[7:0]
0x92[3:0], 0x93[7:0]
0x94[3:0], 0x95[7:0]
0x96[3:0], 0x97[7:0]
0x98[3:0], 0x99[7:0]
0x9A[3:0], 0x9B[7:0]
0x9C[3:0], 0x9D[7:0]
0x9E[3:0], 0x9F[7:0]
0xA0[5:0]
0xA1[5:0]
0xA2[5:0]
0xA3[5:0]
0xA4[5:0]
0xA5[5:0]
0xA6[5:0]
0xA7[5:0]
0xA8[5:0]
0xA9[5:0]
0xAA[5:0]
Adjusts
SAV position
EAV position
HSync start position
HSync width
DE start position
DE end position
VSync/Field versus HSync position. Can be
used when VSync/Field is approximately
coincident with HSync.
VSync/Field versus HSync position. Can be
used when VSync/Field is approximately
midway through HSync.
656 code 'V' bit low-to-high transition position
for odd field
656 code 'V' bit low-to-high transition position
for even field
656 code 'V' bit low-to-high transition position
for odd field
656 code 'V' bit low-to-high transition position
for even field
656 code 'F' transition position for odd field
656 code 'F' transition position for even field
Field pin transition position for odd field
Field pin transition position for even field
VSync start position for odd field
VSync start position for even field
VSync end position for odd field
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ADV7604