Asynchronous Mode; Addressing Scheme - Case When The Expansion Bus Is Interfaced To Two 16-Bit Fifos - Texas Instruments TMS320C6201 Reference Manual

Expansion Bus I/O Port Operation
Figure 8–6. Example of the Expansion Bus Interface to Two 16-Bit FIFOs
Table 8–7. Addressing Scheme – Case When the Expansion Bus is Interfaced to Two
16-Bit FIFOs
Logical Address
FIFO #1 Address
FIFO #2 Address
Physical Address
8.4.1

Asynchronous Mode

8-12
XFCLK
XOE
XD[15:0]
XD[31:0]
XD[31:0]
XD[31:16]
XCE
XRE
XA[2]
A[31:6] A5
X X
X X
XA5
The asynchronous cycles of the expansion bus are identical to the
asynchronous cycles provided by the EMIF. During asynchronous peripheral
accesses, XRDY acts as an active-high ready input and XBE[3:0]/XA[5:2]
operate as address signals XA[5:2]. The remaining asynchronous peripheral
signals operate exactly like their EMIF counterpart. For a complete
description, see the External Memory Interface section. The following
minimum values apply to the asynchronous parameters:
SETUP + STROBE + HOLD
J
SETUP 1
J
STROBE
If XRDY used to extend STROBE then HOLD
FIFO #1
CLK WEN
OE
D[15:0]
FIFO #2
CLK WEN
OE
D[15:0]
A4 A3
X X
X X
XA4 XA3
3
1
REN
REN
A2 A1
0 0
1 1
XA2
2.
A0
0
0