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26.3.1
Clock Timing
Table 26-5 lists the clock timing
Table 26-5 Clock Timing
Condition:
PV
= 4.5 V to 5.5 V, AV
CC
V
= AV
SS
T
= –20°C to +75°C (regular specifications), T
a
specifications)
Item
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Clock oscillator settling
time at reset (crystal)
Clock oscillator settling time in
software standby (crystal)
External clock output stabilization
delay time
32 kHz clock oscillation settling time
Sub clock oscillator frequency
Sub clock (ø
) cycle time
SUB
Note: * The input clock frequency should be set to 25 MHz or less. If ø = 25 MHz to 28 MHz, use
the PLL to multiply the frequency (×2 or ×4).
1058
= 4.5 V to 5.5 V, V
CC
= 0 V, ø = 32.768 kHz, 2 to 28 MHz * ,
= PLLV
SS
SS
Symbol
t
cyc
t
CH
t
CL
t
Cr
t
Cf
t
OSC1
t
OSC2
t
DEXT
t
OSC3
f
SUB
t
SUB
= 4.5 V to AV
ref
= –40°C to +85°C (wide-range
a
28MHz
Min
Max
Unit
35.7
500
ns
10
—
ns
10
—
ns
—
5
ns
—
5
ns
10
—
ms
5
—
ms
2
—
ms
—
2
s
32.768
32.768 kHz
µs
30.5
30.5
,
CC
Test Conditions
Figure 26-2
Figure 26-3
Figure 24-3
Figure 26-3
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